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uniquestruct
a4c7f8c6
·
Update catapult script
·
Jul 05, 2018
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dependencies
6f253d50
·
With constraint
·
Jul 20, 2018
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modelsim
b19ae59b
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Changed syscall
·
Jul 31, 2018
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neumann
cbcafbf6
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Without cache through controller
·
Aug 08, 2018
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nomem
e2ed42a7
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No mem synthesize
·
Sep 04, 2018
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external
32268389
·
Synthesize only one div & rem
·
Sep 13, 2018
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csr
c8d0d95c
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Slight modification for synthesis
·
Sep 14, 2018
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coherence
ca1dd791
·
Nope, doesnt work...
·
Sep 28, 2018
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numpy_proba
fe6f0ae4
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Modified the error distribution file to hold more registers
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Oct 31, 2018
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memtrace
ee5db0a5
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improved makefile
·
Jan 21, 2019
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argparser
ddf269a8
·
Modified doCore for catapult
·
Feb 25, 2019
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simple_alu
77a22520
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Modified doCore for catapult
·
Mar 04, 2019
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vivado
c19cebfb
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Modifying caches to make it build with catapult. Current version is not...
·
Apr 15, 2019
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ca_int
9d59e884
·
Corrected some bugs, there are others in ca_int
·
Jun 27, 2019
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cacheAndDiv
d546cd3a
·
Solved (correctly) the bug with syscall. This branch should now pss CI
·
Oct 02, 2019
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butterfly
b711b717
·
Adding test files for fft
·
Oct 10, 2019
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floatingPoint
f774c6f3
·
Merging with branch rv32im
·
Nov 04, 2019
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fault_injection_oldCore
3b5a7d4b
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Adding and mask to ensure that it fits in memory for 4096 words
·
Nov 06, 2019
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revert-9772473a
153d8ece
·
Revert "Revert "Adds expect ALU (does not compile yet)""
·
Nov 26, 2019
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cabaModel
930fb230
·
More caba changes
·
Dec 06, 2019
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