Mentions légales du service
Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
why3
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Deploy
Releases
Container registry
Monitor
Service Desk
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
Why3
why3
Commits
d5aa13c2
Commit
d5aa13c2
authored
7 years ago
by
MARCHE Claude
Browse files
Options
Downloads
Patches
Plain Diff
new test on bitvectors
parent
fe99748b
No related branches found
No related tags found
1 merge request
!2
Isabelle configure realization1
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
examples/tests/bitvector-test.why
+17
-0
17 additions, 0 deletions
examples/tests/bitvector-test.why
with
17 additions
and
0 deletions
examples/tests/bitvector-test.why
+
17
−
0
View file @
d5aa13c2
...
...
@@ -22,3 +22,20 @@ theory TestBv32
let b = asr (lsr ones 1) 16 in nth b 16 = False
end
theory NthConvert
use import mach.int.Int
use bv.BV8
use bv.BV64
use bv.BVConverter_8_64 as BVC
lemma bv8_to_bv64_low:
forall x i. 0 <= i < 8 -> BV64.nth (BVC.toBig x) i = BV8.nth x i
by forall i.
BV64.nth_bv (BVC.toBig x) (BVC.toBig i) = BV8.nth_bv x i
lemma bv8_to_bv64_high:
forall x i. 8 <= i < 64 -> BV64.nth (BVC.toBig x) i = false
end
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment