URSID

Welcome to the URSID git repository

This is the official repository for the URSID project.

What is URSID

URSID is an automatic vulnerable architecture generation tool. By describing an attack scenario on a high-level (using the MITRE technique nomenclature), URSID is able to refine it into several on a procedural level. All of the resulting architectures will be vulnerable to the same attack on a technical level, but procedures (such as exploits available on machines) and secrets (such as passwords) will vary on a machine to machine basis.

Uses for URSID as a tool for researchers include:

• Customized honeypot generation, for instance in order to match a known attacker's prefered modus operandi.
• Cyber-range/CTF/red-team training applications, including AI attackers.
• Log and dataset generation corresponding to specific attacks.

Documentation

The documentation can be found here.

Features

• Framework for the formalization of attack scenarios on a technical level.
• Backtracking algorithm to refine one of those scenarios into several instances on a procedural level.
• Deployment of one of these instances into virtual machine architectures.
• An example attack scenario which can be refined, deployed then attacked from start to finish.
• A docker showcase of the refinement process.

Requirements

• Python 3.10 or later.

If you wish to also deploy the generated architectures:

• Vagrant 2.2.19 or later.
• Ansible. 2.12 or later.
• VirtualBox v6.1.32 or later.

Try it yourself!

Quick use

If you don't have Vagrant/Ansible/Virtualbox and just wish to see the refinement process:

pip install -r requirements.txt
python3 main.py ./example_scenario/cerbere_json.json --refinement_only

If you have all requirements and wish to deploy the resulting architectures:

pip install -r requirements.txt
python3 main.py ./example_scenario/cerbere_json.json 
cd output/scenario_0
vagrant up

Please refer to the documentation for more detailed usage instructions.

Contributors

• Main contributor and repository maintainer: Pierre-Victor BESSON, PhD student at CentraleSupelec/INRIA.
• Design contributions: Valérie VIET TRIEM TONG, Gilles GUETTE, Erwan ABGRALL and Guillaume PIOLLE, all PhD supervisors.
• Code contribution (Apiculteur): Gireg Maury and Alexandre Monroche, former CentraleSupelec students.
• Special thanks: Alexandre Sanchez.

Questions? Contact pierre-victor.besson@inria.fr