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Created with Raphaël 2.2.017May13127622Apr1727Mar22updated applicationsmainmainProgramming FPGAs with vivado as OpenFPGALoader is not availableUpdate for synthesis at schoolUpdate MakefileUpdate riscv_logo.cUpdate .gitignorelarge updateUpdate for synthesisUpdates for synthesisMerge branch 'main' of https://gitlab.inria.fr/bertrand.le-gal/ENSSAT-RISCV-design-studentIPsUpdate bit_reverse.cThe logo applications (on OLED screen) that can't work yet (SoC modifications are required)Create bit_reverse.cThe bit-reversal exempleBasic tests for your RISC-V coreUpdateUpdate README.mdUpdate main.cUpdate README.mdMerge branch 'main' of https://gitlab.inria.fr/bertrand.le-gal/ENSSAT-RISCV-design-studentUpdateOups !Update .gitignoreUpdateCreate .touchCreate enssat-course.pdfUpdate riscv_types.vhdUpdate riscv_types.vhdpdf docsfirst commitCreate .gitignoreInitial commit