syfala

#Syfala project 

Syfala (_Synthétiseurs faible latence _in French), started as small project funded by FIL (Fédération Informatique de Lyon), then grew up and provided an ANR project (FAST) and (hopefully) the creation of an INSA-INRIA-GRAME associated team. The objective of this tool is to provide and easy compilation from Faust language to FPGA in order to obtain ultra-low latency response for audio processing. This has application in digital lutherie, active actoustic control, vibration control, etc. 

This repository presents several "versions" of Syfala, the different version correspond to different interfaces of the IP generated from Faust.

# Syfala repo
 
Syfala gitlab repository, see documentation in file syfala-getting-started.pdf


## Disclaimer
**v1 to v4** uses vivado 2019.1 version (and the associated vivado_hls)  
**v1-four-axi**: first version (Gero's version)  
**v2-one-axi**: second version using only one axi IP.  
**v3-debug-i2s**: third version: v2+provides GPIO pins to debug I2S  

**From v4**, the I2S is corrected to perform a real hand-shake with the Faust IP
There remain a problem when the FPGA uses the external memory: the latency is  too long (it seems)


**From v5** we use vivado 2020.2 version, together with vitis_hls and vitis (2020.2).  
**From v5** we use petalinux to have a real hardware/software design. Petalinux should be the same version as Vivado, so use petalinux v2020.2.  

## Getting started (v5.5 and sooner)

Clone the repository and go inside the choosen version.  
From the v5.5, everything is handle with one makefile.  
  
You can choose to use your own Petalinux directory or create one from a provided BSP.  

#### Create a Petalinux project (default)

If you don't already have a petalinux project on your computer or don't want to modify it, you can create a new one from a provided BSP.  
Set the `PETALINUX_DIR` variable in the makefile to the 'petalinux' folder of your syfala directory.  
It should be OK as default:  

This folder contains the BSP which will be used to create the project.  
Create a project from a BSP is faster but it's still few hours, don't be in a rush...

#### Use your own petalinux directory

Use your own directory allows you to avoid rebuilding a petalinux (which can take several hours).  
You can use the same Petalinux directory for each version of syfala.  
For that, just set the `PETALINUX_DIR` variable in the makefile to your Petalinux directory (absolute path)  

### Build the project

#### Auto
To build the project and create (if you chose it), build and boot Petalinux:  

Make sure that JP5 is on JTAG position and that the zybo is connected, reset and trun on.  
Then, go to the ****Upload and connect**** section.  

#### Manually

To make the hardware files:  

  
To build and eventually create the Petalinux project:  

  
To boot petalinux on Zybo:  

Ensure that JP5 is on JTAG position and that the zybo is connected and reset.  
  

### Upload and connect

#### With SSH

If you want to use SSH to communicate with the board, please find the board IP and set the `ZYBO_IP_ADDRESS` variable in the makefile.  
Then, use:  

To download and connect to the board with SSH.  
Once the login prompt appears:

#### With UART (not sure que ca marche)

Make sure that `lrzsz` is installed on your computer  

Use `minicom` in sudo mode to connect to the board (only minicom works).  
Once the login prompt appears:

Once you are logged in, type:  

If the command is not recognized, use the SSH method.  
Else, use `ctrl+a, s`, select zmodem, and find the .elf file in build/sw_export and upload it.  

### Execute

On the board's shell:  

### Clean

## Version

Please make sure to use the corresponding version of faust and vivado.

### v5.5-stable (latest)

Same as v5.4.  
I2C and I2S transceivers are stablizied.
The scale factor is controlled on ARM and set to 0x400000 by default to patch de SSM bug...

*Vivado Version: 2020.2*  
*FAUST Version: 2.31.1 (-uim and new -os version)*

### v5.4-sinewave-generic

Use of petalinux with generic app on ARM based on arm.c architecture file to control IP.  
Compute the controlmydsp function on the ARM and send icontrol and fcontrol value.  
Generic compilation, no need to modify computemydsp

*Vivado Version: 2020.2*  
*FAUST Version: 2.31.1 (-uim and new -os version)*
#### v5.3.2-sinewave-arm-newfaust

*Same as v5.3 but this one works with Faust v2.31 (which change the -os option and make other version not compatible)*  
Use of petalinux with generic app on ARM based on arm.c architecture file to control IP.  
Compute the controlmydsp function on the ARM and send icontrol and fcontrol value.  
The controlmydsp function on arm.c has to be modified by hand because of the non generic faust compilation  

*Vivado Version: 2020.2*  
*FAUST Version: 2.31.1 (-uim and new -os version)*

#### v5.3-sinewave-arm
Use of petalinux with generic app on ARM based on arm.c architecture file to control IP.  
Compute the controlmydsp function on the ARM and send icontrol and fcontrol value.  
The controlmydsp function on arm.c has to be modified by hand because of the non generic faust compilation  

*Vivado Version: 2020.2*  
*FAUST Version:  2.30.8 (-uim version)*

#### v5.2-petalinux-2
Use of petalinux with generic app on ARM based on arm.c architecture file to control IP.  
The app directly send value of controler to the FPGA, contromydsp is on the FPGA	

*Vivado Version: 2020.2*  
*FAUST Version: 2.30.8 (-uim version)*

#### v5.1-petalinux-1
Use of petalinux with non generic app on ARM to control IP.  
The app directly send value of controler to the FPGA, contromydsp is on the FPGA  

*Vivado Version: 2020.2*  
*FAUST Version: 2.30.2 (no -uim)*

#### v4.3-button-trigger
Use a switch to trigger the first button define on the faust DSP (and no axi)  

*Vivado Version: 2019.1*  
*FAUST Version: 2.30.2 (no -uim)*

#### v4.2-hand-shake-one-axi:
Uses one axi bus for storing samples  
Does not work correctly, it has to be debugged yet.

*Vivado Version: 2019.1*  
*FAUST Version: 2.30.2 (no -uim)*

#### v4.1-hand-shake-no-axi:
Does not use  the external memory, it only uses block Ram for all memory  
Is correct on example that do not use to many samples (ex: KarpusStrong)  

*Vivado Version: 2019.1*  
*FAUST Version: 2.30.2 (no -uim)*
   

## Petalinux
For HW/SW design you need, in addition to vivado tools,  to install petalinux distribution on your machine.  
Directory petalinux can help you install petalinux on your machine (warning: 5OGB needed) and build a petalinux_syfala distribution.  
Please look at petalinux/README.txt for that.  
Once petalinux_syfala installed, you need to set up petalinux_syfala directory in current directory Makefile in order to be able to run the "make boot" directory.  
  
## Vivado 2019 backward compatibility
From v5 we use vivado 2020.2 version, together with vitis_hls and vitis (2020.2)

It's possible to use vivado 2020.2 with v4 or older, just do this:

1. Call *vitis_hls* instead of *vivado_hls* in the makefile
2. In *fpga.cpp*, rename all vector argument with a "**_V**" at the end: 
   
```ap_int<24> in_left   =>    ap_int<24> in_left_V```


See README_maj_2020.txt for more info

## TODO
- [x] Map physical switches to IP
- [x] Use petalinux
- [x] Control on ARM
- [ ] Init on ARM
- [ ] Use external memory