Commit f1546983 authored by Stefan Berghofer's avatar Stefan Berghofer
Browse files

Added more realizations

parent 33b8c267
......@@ -73,15 +73,8 @@ theory int.MinMax
syntax function max "<app><const name=\"Orderings.ord_class.max\"/>%1%2</app>"
end
theory int.EuclideanDivision
syntax function div "<app><const name=\"Divides.div_class.div\"/>%1%2</app>"
syntax function mod "<app><const name=\"Divides.div_class.mod\"/>%1%2</app>"
remove prop Div_mod
remove prop Div_bound
remove prop Mod_bound
remove prop Mod_1
remove prop Div_1
theory int.Exponentiation
syntax function power "<app><const name=\"Power.power_class.power\"/>%1<app><const name=\"Int.nat\"/>%2</app></app>"
end
theory list.List
......@@ -125,6 +118,7 @@ theory map.Map
syntax function ([]) "<app>%1%2</app>"
syntax function set "<app><const name=\"Fun.fun_upd\"/>%1%2%3</app>"
syntax function ([<-]) "<app><const name=\"Fun.fun_upd\"/>%1%2%3</app>"
syntax function const "<app><const name=\"_type_constraint_\"><fun>%t0%t0</fun></const><abs name=\"\"><type name=\"dummy\"/>%1</abs></app>"
end
theory set.SetGen
......
theory Why3
imports Why3_Set Why3_List
imports
Why3_Map
Why3_Set
Why3_List
Why3_Int
begin
end
theory Why3_Int
imports Why3_Setup
begin
section {* Integers and the basic operators *}
why3_open "int/Int.xml"
why3_vc Comm by simp
why3_vc Comm1 by simp
why3_vc Assoc by simp
why3_vc Assoc1 by simp
why3_vc Unitary by simp
why3_vc Inv_def_l by simp
why3_vc Inv_def_r by simp
why3_vc Unit_def_l by simp
why3_vc Unit_def_r by simp
why3_vc Mul_distr_l by (simp add: ring_distribs)
why3_vc Mul_distr_r by (simp add: ring_distribs)
why3_vc infix_mn_def by simp
why3_vc NonTrivialRing by simp
why3_vc infix_lseq_def by auto
why3_vc Refl by simp
why3_vc Trans using assms by simp
why3_vc Total by auto
why3_vc Antisymm using assms by simp
why3_vc ZeroLessOne by simp
why3_vc CompatOrderAdd using assms by simp
why3_vc CompatOrderMult using assms by (rule mult_right_mono)
why3_end
section {* Absolute Value *}
why3_open "int/Abs.xml"
why3_vc abs_def by simp
why3_vc Abs_le by auto
why3_vc Abs_pos by simp
why3_end
section {* Minimum and Maximum *}
why3_open "int/MinMax.xml"
why3_vc Max_x using assms by simp
why3_vc Max_y using assms by simp
why3_vc Max_sym by simp
why3_vc Max_is_ge by simp_all
why3_vc Max_is_some by auto
why3_vc Min_x using assms by simp
why3_vc Min_y using assms by simp
why3_vc Min_sym by simp
why3_vc Min_is_le by simp_all
why3_vc Min_is_some by auto
why3_end
section {* Euclidean Division *}
definition ediv :: "int \<Rightarrow> int \<Rightarrow> int" (infixl "ediv" 70) where
"a ediv b = sgn b * (a div \<bar>b\<bar>)"
definition emod :: "int \<Rightarrow> int \<Rightarrow> int" (infixl "emod" 70) where
"a emod b = a mod \<bar>b\<bar>"
why3_open "int/EuclideanDivision.xml"
constants
div = ediv
mod = emod
why3_vc Div_1 by (simp add: ediv_def)
why3_vc Div_1_left using assms by (simp add: ediv_def div_pos_pos_trivial)
why3_vc Div_inf using assms by (simp add: ediv_def div_pos_pos_trivial)
why3_vc Div_inf_neg
using assms
by (cases "x = y") (simp_all add: ediv_def
zdiv_zminus1_eq_if div_pos_pos_trivial mod_pos_pos_trivial)
why3_vc Div_mod
by (simp add: ediv_def emod_def mult_assoc [symmetric] abs_sgn)
why3_vc Div_mult using assms by (simp add: ediv_def add_commute)
why3_vc Div_bound
proof -
from assms show ?C1
by (simp add: ediv_def pos_imp_zdiv_nonneg_iff)
show ?C2
proof (cases "x = 0")
case False
show ?thesis
proof (cases "y = 1")
case False
with assms `x \<noteq> 0` have "x div y < x"
by (simp add: int_div_less_self)
with assms show ?thesis by (simp add: ediv_def)
qed (simp add: ediv_def)
qed (simp add: ediv_def)
qed
why3_vc Div_minus1_left
using assms
by (simp only: zdiv_zminus1_eq_if ediv_def)
(simp add: div_pos_pos_trivial mod_pos_pos_trivial)
why3_vc Mod_0 by (simp add: emod_def)
why3_vc Mod_1 by (simp add: emod_def)
why3_vc Mod_1_left using assms by (simp add: emod_def mod_pos_pos_trivial)
why3_vc Mod_minus1_left
using assms
by (simp only: emod_def zmod_zminus1_eq_if) (simp add: mod_pos_pos_trivial)
why3_vc Mod_mult using assms by (simp add: emod_def add_commute)
why3_vc Mod_bound using assms by (simp_all add: emod_def)
why3_end
section {* Computer Division *}
definition cdiv :: "int \<Rightarrow> int \<Rightarrow> int" (infixl "cdiv" 70) where
"a cdiv b = sgn a * sgn b * (\<bar>a\<bar> div \<bar>b\<bar>)"
definition cmod :: "int \<Rightarrow> int \<Rightarrow> int" (infixl "cmod" 70) where
"a cmod b = sgn a * (\<bar>a\<bar> mod \<bar>b\<bar>)"
why3_open "int/ComputerDivision.xml"
constants
div = cdiv
mod = cmod
why3_vc Div_1 by (simp add: cdiv_def mult_sgn_abs)
why3_vc Div_inf using assms by (simp add: cdiv_def div_pos_pos_trivial)
why3_vc Div_sign_neg
using assms
by (cases "x = 0") (simp_all add: cdiv_def
zdiv_zminus1_eq_if div_nonpos_pos_le0 pos_imp_zdiv_neg_iff)
why3_vc Div_sign_pos
using assms
by (cases "x = 0")
(simp_all add: cdiv_def pos_imp_zdiv_nonneg_iff)
why3_vc Div_mod
proof -
have "y * (sgn x * sgn y * (\<bar>x\<bar> div \<bar>y\<bar>)) + sgn x * (\<bar>x\<bar> mod \<bar>y\<bar>) =
sgn x * (y * sgn y * (\<bar>x\<bar> div \<bar>y\<bar>) + \<bar>x\<bar> mod \<bar>y\<bar>)"
by (simp add: ring_distribs)
then show ?thesis
by (cases "x = 0") (simp_all add: cdiv_def cmod_def abs_sgn
sgn_times [symmetric] order.strict_iff_order)
qed
why3_vc Div_mult
proof (cases "y = 0")
case False
with assms show ?thesis
by (cases "z = 0")
(simp_all add: cdiv_def add_commute add_pos_pos mult_nonneg_nonneg mult_pos_pos)
qed simp
why3_vc Div_bound
proof -
from assms show ?C1
by (simp add: cdiv_def pos_imp_zdiv_nonneg_iff sgn_if)
show ?C2
proof (cases "x = 0")
case False
show ?thesis
proof (cases "y = 1")
case False
with assms `x \<noteq> 0` have "x div y < x"
by (simp add: int_div_less_self)
with assms show ?thesis by (simp add: cdiv_def sgn_if)
qed (simp add: cdiv_def sgn_if)
qed (simp add: cdiv_def)
qed
why3_vc Mod_1 by (simp add: cmod_def)
why3_vc Mod_inf using assms by (simp add: cmod_def mod_pos_pos_trivial sgn_if)
why3_vc Mod_mult
proof (cases "y = 0")
case False
with assms show ?thesis
by (cases "z = 0") (simp_all add: cmod_def
add_commute add_pos_pos mult_nonneg_nonneg mult_pos_pos)
qed simp
why3_vc Mod_bound
proof -
from assms show ?C1
by (auto simp add: cmod_def sgn_if intro: less_le_trans [of _ 0])
from assms show ?C2
by (auto simp add: cmod_def sgn_if intro: le_less_trans [of _ 0])
qed
why3_vc Mod_sign_neg using assms by (simp add: cmod_def sgn_if)
why3_vc Mod_sign_pos using assms by (simp add: cmod_def sgn_if)
why3_vc Rounds_toward_zero
proof (cases "x = 0")
case False
then have "\<bar>sgn x\<bar> = 1" by (simp add: sgn_if)
have "sgn x * sgn y * (\<bar>x\<bar> div \<bar>y\<bar>) * y =
sgn x * (y * sgn y * (\<bar>x\<bar> div \<bar>y\<bar>))" (is "?l = ?r")
by simp
then have "\<bar>?l\<bar> = \<bar>?r\<bar>" by (simp (no_asm_simp))
also note abs_sgn [symmetric]
also note abs_mult
also have "\<bar>y\<bar> * (\<bar>x\<bar> div \<bar>y\<bar>) \<le> \<bar>y\<bar> * (\<bar>x\<bar> div \<bar>y\<bar>) + \<bar>x\<bar> mod \<bar>y\<bar>"
by (rule add_increasing2) (simp_all add: assms)
with assms have "\<bar>\<bar>y\<bar> * (\<bar>x\<bar> div \<bar>y\<bar>)\<bar> \<le> \<bar>\<bar>y\<bar> * (\<bar>x\<bar> div \<bar>y\<bar>) + \<bar>x\<bar> mod \<bar>y\<bar>\<bar>"
by (simp add: mult_nonneg_nonneg pos_imp_zdiv_nonneg_iff)
finally show ?thesis using `\<bar>sgn x\<bar> = 1`
by (simp add: cdiv_def)
qed (simp add: cdiv_def)
why3_end
section {* Division by 2 *}
why3_open "int/Div2.xml"
why3_vc div2
by (rule exI [of _ "x div 2"]) auto
why3_end
section {* Power of an integer to an integer *}
why3_open "int/Power.xml"
why3_vc Power_0 by simp
why3_vc Power_1 by simp
why3_vc Power_s using assms by (simp add: nat_add_distrib)
why3_vc Power_s_alt using assms by (simp add: nat_diff_distrib power_Suc [symmetric])
why3_vc Power_sum using assms by (simp add: nat_add_distrib power_add)
why3_vc Power_mult using assms by (simp add: nat_mult_distrib power_mult)
why3_vc Power_mult2 by (simp add: power_mult_distrib)
why3_end
end
......@@ -28,6 +28,9 @@ section {* Nth element of a list *}
why3_open "Nth.xml"
lemma nth_eq: "0 \<le> i \<Longrightarrow> nat i < length xs \<Longrightarrow> nth i xs = Some (xs ! nat i)"
by (induct xs arbitrary: i) (auto simp add: nat_diff_distrib)
why3_end
......@@ -72,4 +75,87 @@ qed
why3_end
section {* Head and tail *}
why3_open "HdTl.xml"
why3_end
section {* Relation between head, tail, and nth *}
why3_open "NthHdTl.xml"
why3_vc Nth_tl
using assms
by (simp add: tl_def split add: list.split_asm)
why3_vc Nth0_head
by (simp add: hd_def split add: list.split)
why3_end
section {* Appending two lists *}
why3_open "Append.xml"
why3_vc infix_plpl_def by (simp split add: list.split)
why3_vc Append_assoc by simp
why3_vc Append_l_nil by simp
why3_vc Append_length by simp
why3_vc mem_append by simp
why3_vc mem_decomp
using assms
by (simp add: in_set_conv_decomp)
why3_end
why3_open "NthLengthAppend.xml"
why3_vc nth_append_1
proof (cases "0 \<le> i")
case True
with assms have "nat i < length l1" by simp
with True show ?thesis
by (simp add: nth_eq nth_append)
next
case False
then show ?thesis by (simp add: nth_none_1)
qed
why3_vc nth_append_2
proof (cases "nat i < length (l1 @ l2)")
case True
with assms show ?thesis
by (auto simp add: nth_eq nth_append nat_diff_distrib)
next
case False
with assms show ?thesis by (simp add: nth_none_2)
qed
why3_end
section {* Reversing a list *}
why3_open "Reverse.xml"
why3_vc reverse_def by (simp split add: list.split)
why3_vc Reverse_length by simp
why3_vc reverse_append by simp
why3_vc reverse_reverse by simp
why3_end
end
theory Why3_Map
imports Why3_Setup
begin
why3_open "Map.xml"
why3_vc Const by simp
why3_vc Select_eq
using assms
by simp
why3_vc Select_neq
using assms
by simp
why3_end
end
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