Commit b67fb7c0 authored by Andrei Paskevich's avatar Andrei Paskevich

update sessions

parent 61127a19
This diff is collapsed.
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
locfile="../algo64.mlw" locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19" loclnum="37" loccnumb="10" loccnume="19"
expl="VC for quicksort" expl="VC for quicksort"
sum="fcd077bab8a5898e2fec68c14d231ebf" sum="11e0ec38983b8ef38413190f7b000838"
proved="true" proved="true"
expanded="true" expanded="true"
shape="iasorted_subV1V2ainfix +V3c1Aapermut_subV1V1V2ainfix +V3c1asorted_subV8V2ainfix +V3c1Aapermut_subV1V8V2ainfix +V3c1Aapermut_subV7V8V2ainfix +V3c1Iasorted_subV8V5ainfix +V3c1Aapermut_subV7V8V5ainfix +V3c1Aainfix <=c0V0FAainfix <V3V0Aainfix <=V5V3Aainfix <=c0V5Aainfix <ainfix -V3V5ainfix -V3V2Aainfix <=c0ainfix -V3V2Aapermut_subV6V7V2ainfix +V3c1Iasorted_subV7V2ainfix +V4c1Aapermut_subV6V7V2ainfix +V4c1Aainfix <=c0V0FAainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Aainfix <ainfix -V4V2ainfix -V3V2Aainfix <=c0ainfix -V3V2Iainfix >=agetV6V10V9Iainfix <=V10V3Aainfix <=V5V10FAainfix =agetV6V11V9Iainfix <V11V5Aainfix <V4V11FAainfix <=agetV6V12V9Iainfix <=V12V4Aainfix <=V2V12FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FAainfix <V3V0Aainfix <V2V3Aainfix <=c0V2ainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F"> shape="iasorted_subV1V2ainfix +V3c1Aapermut_subV1V1V2ainfix +V3c1asorted_subV8V2ainfix +V3c1Aapermut_subV1V8V2ainfix +V3c1Aapermut_subV7V8V2ainfix +V3c1Iasorted_subV8V5ainfix +V3c1Aapermut_subV7V8V5ainfix +V3c1Aainfix <=c0V0FAainfix <V3V0Aainfix <=V5V3Aainfix <=c0V5Aainfix <ainfix -V3V5ainfix -V3V2Aainfix <=c0ainfix -V3V2Aapermut_subV6V7V2ainfix +V3c1Iasorted_subV7V2ainfix +V4c1Aapermut_subV6V7V2ainfix +V4c1Aainfix <=c0V0FAainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Aainfix <ainfix -V4V2ainfix -V3V2Aainfix <=c0ainfix -V3V2Iainfix >=agetV6V10V9Iainfix <=V10V3Aainfix <=V5V10FAainfix =agetV6V11V9Iainfix <V11V5Aainfix <V4V11FAainfix <=agetV6V12V9Iainfix <=V12V4Aainfix <=V2V12FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FAainfix <V3V0Aainfix <V2V3Aainfix <=c0V2ainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F">
...@@ -43,7 +43,7 @@ ...@@ -43,7 +43,7 @@
locfile="../algo64.mlw" locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19" loclnum="37" loccnumb="10" loccnume="19"
expl="1. precondition" expl="1. precondition"
sum="860773cc3127cc7d9bf3ac6fb63b2e56" sum="1a91e33b4ccc5d2b06db73cacadca3df"
proved="true" proved="true"
expanded="true" expanded="true"
shape="preconditionainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F"> shape="preconditionainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F">
...@@ -63,7 +63,7 @@ ...@@ -63,7 +63,7 @@
locfile="../algo64.mlw" locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19" loclnum="37" loccnumb="10" loccnume="19"
expl="2. variant decrease" expl="2. variant decrease"
sum="bdbc1a16c7d2b31121555597446c2de3" sum="da59ba895708f566dd6d4489d1abb8b8"
proved="true" proved="true"
expanded="true" expanded="true"
shape="variant decreaseainfix <ainfix -V4V2ainfix -V3V2Aainfix <=c0ainfix -V3V2Iainfix >=agetV6V8V7Iainfix <=V8V3Aainfix <=V5V8FAainfix =agetV6V9V7Iainfix <V9V5Aainfix <V4V9FAainfix <=agetV6V10V7Iainfix <=V10V4Aainfix <=V2V10FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F"> shape="variant decreaseainfix <ainfix -V4V2ainfix -V3V2Aainfix <=c0ainfix -V3V2Iainfix >=agetV6V8V7Iainfix <=V8V3Aainfix <=V5V8FAainfix =agetV6V9V7Iainfix <V9V5Aainfix <V4V9FAainfix <=agetV6V10V7Iainfix <=V10V4Aainfix <=V2V10FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F">
...@@ -83,7 +83,7 @@ ...@@ -83,7 +83,7 @@
locfile="../algo64.mlw" locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19" loclnum="37" loccnumb="10" loccnume="19"
expl="3. precondition" expl="3. precondition"
sum="d69238372f211d5a042b1fa5f01c857d" sum="9c534646a73c85a15840090ce3ccc11a"
proved="true" proved="true"
expanded="true" expanded="true"
shape="preconditionainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Iainfix >=agetV6V8V7Iainfix <=V8V3Aainfix <=V5V8FAainfix =agetV6V9V7Iainfix <V9V5Aainfix <V4V9FAainfix <=agetV6V10V7Iainfix <=V10V4Aainfix <=V2V10FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F"> shape="preconditionainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Iainfix >=agetV6V8V7Iainfix <=V8V3Aainfix <=V5V8FAainfix =agetV6V9V7Iainfix <V9V5Aainfix <V4V9FAainfix <=agetV6V10V7Iainfix <=V10V4Aainfix <=V2V10FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F">
...@@ -103,7 +103,7 @@ ...@@ -103,7 +103,7 @@
locfile="../algo64.mlw" locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19" loclnum="37" loccnumb="10" loccnume="19"
expl="4. assertion" expl="4. assertion"
sum="dd52b66e8a6d0c488c58a082a068cbdb" sum="a2ec830713293a1edfcfbecda44bcd78"
proved="true" proved="true"
expanded="true" expanded="true"
shape="assertionapermut_subV6V7V2ainfix +V3c1Iasorted_subV7V2ainfix +V4c1Aapermut_subV6V7V2ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Iainfix >=agetV6V9V8Iainfix <=V9V3Aainfix <=V5V9FAainfix =agetV6V10V8Iainfix <V10V5Aainfix <V4V10FAainfix <=agetV6V11V8Iainfix <=V11V4Aainfix <=V2V11FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F"> shape="assertionapermut_subV6V7V2ainfix +V3c1Iasorted_subV7V2ainfix +V4c1Aapermut_subV6V7V2ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Iainfix >=agetV6V9V8Iainfix <=V9V3Aainfix <=V5V9FAainfix =agetV6V10V8Iainfix <V10V5Aainfix <V4V10FAainfix <=agetV6V11V8Iainfix <=V11V4Aainfix <=V2V11FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F">
...@@ -123,7 +123,7 @@ ...@@ -123,7 +123,7 @@
locfile="../algo64.mlw" locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19" loclnum="37" loccnumb="10" loccnume="19"
expl="5. variant decrease" expl="5. variant decrease"
sum="6b37fdc9b8ba1d01b74a77d867dc1af8" sum="1d8af92cbd4765778bf722473a0bd96b"
proved="true" proved="true"
expanded="true" expanded="true"
shape="variant decreaseainfix <ainfix -V3V5ainfix -V3V2Aainfix <=c0ainfix -V3V2Iapermut_subV6V7V2ainfix +V3c1Iasorted_subV7V2ainfix +V4c1Aapermut_subV6V7V2ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Iainfix >=agetV6V9V8Iainfix <=V9V3Aainfix <=V5V9FAainfix =agetV6V10V8Iainfix <V10V5Aainfix <V4V10FAainfix <=agetV6V11V8Iainfix <=V11V4Aainfix <=V2V11FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F"> shape="variant decreaseainfix <ainfix -V3V5ainfix -V3V2Aainfix <=c0ainfix -V3V2Iapermut_subV6V7V2ainfix +V3c1Iasorted_subV7V2ainfix +V4c1Aapermut_subV6V7V2ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Iainfix >=agetV6V9V8Iainfix <=V9V3Aainfix <=V5V9FAainfix =agetV6V10V8Iainfix <V10V5Aainfix <V4V10FAainfix <=agetV6V11V8Iainfix <=V11V4Aainfix <=V2V11FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F">
...@@ -143,7 +143,7 @@ ...@@ -143,7 +143,7 @@
locfile="../algo64.mlw" locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19" loclnum="37" loccnumb="10" loccnume="19"
expl="6. precondition" expl="6. precondition"
sum="c4bcca39da032ce4005ea1d0c439ac35" sum="f940cea88b26a332531aca899c6c48dd"
proved="true" proved="true"
expanded="true" expanded="true"
shape="preconditionainfix <V3V0Aainfix <=V5V3Aainfix <=c0V5Iapermut_subV6V7V2ainfix +V3c1Iasorted_subV7V2ainfix +V4c1Aapermut_subV6V7V2ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Iainfix >=agetV6V9V8Iainfix <=V9V3Aainfix <=V5V9FAainfix =agetV6V10V8Iainfix <V10V5Aainfix <V4V10FAainfix <=agetV6V11V8Iainfix <=V11V4Aainfix <=V2V11FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F"> shape="preconditionainfix <V3V0Aainfix <=V5V3Aainfix <=c0V5Iapermut_subV6V7V2ainfix +V3c1Iasorted_subV7V2ainfix +V4c1Aapermut_subV6V7V2ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Iainfix >=agetV6V9V8Iainfix <=V9V3Aainfix <=V5V9FAainfix =agetV6V10V8Iainfix <V10V5Aainfix <V4V10FAainfix <=agetV6V11V8Iainfix <=V11V4Aainfix <=V2V11FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F">
...@@ -163,7 +163,7 @@ ...@@ -163,7 +163,7 @@
locfile="../algo64.mlw" locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19" loclnum="37" loccnumb="10" loccnume="19"
expl="7. assertion" expl="7. assertion"
sum="7ad64f8644601ffd7ea74cdf1b5d59b8" sum="e0eccde7bb5f060921081ffcb2209d82"
proved="true" proved="true"
expanded="true" expanded="true"
shape="assertionapermut_subV7V8V2ainfix +V3c1Iasorted_subV8V5ainfix +V3c1Aapermut_subV7V8V5ainfix +V3c1Aainfix <=c0V0FIainfix <V3V0Aainfix <=V5V3Aainfix <=c0V5Iapermut_subV6V7V2ainfix +V3c1Iasorted_subV7V2ainfix +V4c1Aapermut_subV6V7V2ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Iainfix >=agetV6V10V9Iainfix <=V10V3Aainfix <=V5V10FAainfix =agetV6V11V9Iainfix <V11V5Aainfix <V4V11FAainfix <=agetV6V12V9Iainfix <=V12V4Aainfix <=V2V12FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F"> shape="assertionapermut_subV7V8V2ainfix +V3c1Iasorted_subV8V5ainfix +V3c1Aapermut_subV7V8V5ainfix +V3c1Aainfix <=c0V0FIainfix <V3V0Aainfix <=V5V3Aainfix <=c0V5Iapermut_subV6V7V2ainfix +V3c1Iasorted_subV7V2ainfix +V4c1Aapermut_subV6V7V2ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Iainfix >=agetV6V10V9Iainfix <=V10V3Aainfix <=V5V10FAainfix =agetV6V11V9Iainfix <V11V5Aainfix <V4V11FAainfix <=agetV6V12V9Iainfix <=V12V4Aainfix <=V2V12FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F">
...@@ -183,7 +183,7 @@ ...@@ -183,7 +183,7 @@
locfile="../algo64.mlw" locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19" loclnum="37" loccnumb="10" loccnume="19"
expl="8. postcondition" expl="8. postcondition"
sum="d40b41f6a4f1e904835fdbc5cea95039" sum="76e3183894a521560df10aebaa535cfe"
proved="true" proved="true"
expanded="true" expanded="true"
shape="postconditionapermut_subV1V8V2ainfix +V3c1Iapermut_subV7V8V2ainfix +V3c1Iasorted_subV8V5ainfix +V3c1Aapermut_subV7V8V5ainfix +V3c1Aainfix <=c0V0FIainfix <V3V0Aainfix <=V5V3Aainfix <=c0V5Iapermut_subV6V7V2ainfix +V3c1Iasorted_subV7V2ainfix +V4c1Aapermut_subV6V7V2ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Iainfix >=agetV6V10V9Iainfix <=V10V3Aainfix <=V5V10FAainfix =agetV6V11V9Iainfix <V11V5Aainfix <V4V11FAainfix <=agetV6V12V9Iainfix <=V12V4Aainfix <=V2V12FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F"> shape="postconditionapermut_subV1V8V2ainfix +V3c1Iapermut_subV7V8V2ainfix +V3c1Iasorted_subV8V5ainfix +V3c1Aapermut_subV7V8V5ainfix +V3c1Aainfix <=c0V0FIainfix <V3V0Aainfix <=V5V3Aainfix <=c0V5Iapermut_subV6V7V2ainfix +V3c1Iasorted_subV7V2ainfix +V4c1Aapermut_subV6V7V2ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Iainfix >=agetV6V10V9Iainfix <=V10V3Aainfix <=V5V10FAainfix =agetV6V11V9Iainfix <V11V5Aainfix <V4V11FAainfix <=agetV6V12V9Iainfix <=V12V4Aainfix <=V2V12FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F">
...@@ -203,7 +203,7 @@ ...@@ -203,7 +203,7 @@
locfile="../algo64.mlw" locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19" loclnum="37" loccnumb="10" loccnume="19"
expl="9. postcondition" expl="9. postcondition"
sum="4c7142942554e853ce232e51a6ff1f6b" sum="b04b9f2930bbbc20d97026777b784fb1"
proved="true" proved="true"
expanded="true" expanded="true"
shape="postconditionasorted_subV8V2ainfix +V3c1Iapermut_subV7V8V2ainfix +V3c1Iasorted_subV8V5ainfix +V3c1Aapermut_subV7V8V5ainfix +V3c1Aainfix <=c0V0FIainfix <V3V0Aainfix <=V5V3Aainfix <=c0V5Iapermut_subV6V7V2ainfix +V3c1Iasorted_subV7V2ainfix +V4c1Aapermut_subV6V7V2ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Iainfix >=agetV6V10V9Iainfix <=V10V3Aainfix <=V5V10FAainfix =agetV6V11V9Iainfix <V11V5Aainfix <V4V11FAainfix <=agetV6V12V9Iainfix <=V12V4Aainfix <=V2V12FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F"> shape="postconditionasorted_subV8V2ainfix +V3c1Iapermut_subV7V8V2ainfix +V3c1Iasorted_subV8V5ainfix +V3c1Aapermut_subV7V8V5ainfix +V3c1Aainfix <=c0V0FIainfix <V3V0Aainfix <=V5V3Aainfix <=c0V5Iapermut_subV6V7V2ainfix +V3c1Iasorted_subV7V2ainfix +V4c1Aapermut_subV6V7V2ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V2V4Aainfix <=c0V2Iainfix >=agetV6V10V9Iainfix <=V10V3Aainfix <=V5V10FAainfix =agetV6V11V9Iainfix <V11V5Aainfix <V4V11FAainfix <=agetV6V12V9Iainfix <=V12V4Aainfix <=V2V12FEAapermut_subV1V6V2ainfix +V3c1Aainfix <=V5V3Aainfix <V4V5Aainfix <=V2V4Aainfix <=c0V0FIainfix <V3V0Aainfix <V2V3Aainfix <=c0V2Iainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F">
...@@ -218,7 +218,7 @@ ...@@ -218,7 +218,7 @@
locfile="../algo64.mlw" locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19" loclnum="37" loccnumb="10" loccnume="19"
expl="1. postcondition" expl="1. postcondition"
sum="939cbbac569c75bb4ca3e5930ef7d123" sum="1786633a1d7cbf41adc48f293fe5c7a8"
proved="true" proved="true"
expanded="true" expanded="true"
shape="postconditionainfix =agetV8V9agetV8V10Oainfix <agetV8V9agetV8V10Iainfix <V10ainfix +V3c1Aainfix =V9V10Oainfix <V9V10Aainfix =V2V9Oainfix <V2V9FIapermut_subV7V8V2ainfix +V3c1Iainfix =agetV8V11agetV8V12Oainfix <agetV8V11agetV8V12Iainfix <V12ainfix +V3c1Aainfix =V11V12Oainfix <V11V12Aainfix =V5V11Oainfix <V5V11FAapermut_subV7V8V5ainfix +V3c1Aainfix =c0V0Oainfix <c0V0FIainfix <V3V0Aainfix =V5V3Oainfix <V5V3Aainfix =c0V5Oainfix <c0V5Iapermut_subV6V7V2ainfix +V3c1Iainfix =agetV7V13agetV7V14Oainfix <agetV7V13agetV7V14Iainfix <V14ainfix +V4c1Aainfix =V13V14Oainfix <V13V14Aainfix =V2V13Oainfix <V2V13FAapermut_subV6V7V2ainfix +V4c1Aainfix =c0V0Oainfix <c0V0FIainfix <V4V0Aainfix =V2V4Oainfix <V2V4Aainfix =c0V2Oainfix <c0V2Iainfix =V15agetV6V16Oainfix <V15agetV6V16Iainfix =V16V3Oainfix <V16V3Aainfix =V5V16Oainfix <V5V16FAainfix =agetV6V17V15Iainfix <V17V5Aainfix <V4V17FAainfix =agetV6V18V15Oainfix <agetV6V18V15Iainfix =V18V4Oainfix <V18V4Aainfix =V2V18Oainfix <V2V18FEAapermut_subV1V6V2ainfix +V3c1Aainfix =V5V3Oainfix <V5V3Aainfix <V4V5Aainfix =V2V4Oainfix <V2V4Aainfix =c0V0Oainfix <c0V0FIainfix <V3V0Aainfix <V2V3Aainfix =c0V2Oainfix <c0V2Iainfix <V2V3Iainfix <V3V0Aainfix =V2V3Oainfix <V2V3Aainfix =c0V2Oainfix <c0V2Aainfix =c0V0Oainfix <c0V0F"> shape="postconditionainfix =agetV8V9agetV8V10Oainfix <agetV8V9agetV8V10Iainfix <V10ainfix +V3c1Aainfix =V9V10Oainfix <V9V10Aainfix =V2V9Oainfix <V2V9FIapermut_subV7V8V2ainfix +V3c1Iainfix =agetV8V11agetV8V12Oainfix <agetV8V11agetV8V12Iainfix <V12ainfix +V3c1Aainfix =V11V12Oainfix <V11V12Aainfix =V5V11Oainfix <V5V11FAapermut_subV7V8V5ainfix +V3c1Aainfix =c0V0Oainfix <c0V0FIainfix <V3V0Aainfix =V5V3Oainfix <V5V3Aainfix =c0V5Oainfix <c0V5Iapermut_subV6V7V2ainfix +V3c1Iainfix =agetV7V13agetV7V14Oainfix <agetV7V13agetV7V14Iainfix <V14ainfix +V4c1Aainfix =V13V14Oainfix <V13V14Aainfix =V2V13Oainfix <V2V13FAapermut_subV6V7V2ainfix +V4c1Aainfix =c0V0Oainfix <c0V0FIainfix <V4V0Aainfix =V2V4Oainfix <V2V4Aainfix =c0V2Oainfix <c0V2Iainfix =V15agetV6V16Oainfix <V15agetV6V16Iainfix =V16V3Oainfix <V16V3Aainfix =V5V16Oainfix <V5V16FAainfix =agetV6V17V15Iainfix <V17V5Aainfix <V4V17FAainfix =agetV6V18V15Oainfix <agetV6V18V15Iainfix =V18V4Oainfix <V18V4Aainfix =V2V18Oainfix <V2V18FEAapermut_subV1V6V2ainfix +V3c1Aainfix =V5V3Oainfix <V5V3Aainfix <V4V5Aainfix =V2V4Oainfix <V2V4Aainfix =c0V0Oainfix <c0V0FIainfix <V3V0Aainfix <V2V3Aainfix =c0V2Oainfix <c0V2Iainfix <V2V3Iainfix <V3V0Aainfix =V2V3Oainfix <V2V3Aainfix =c0V2Oainfix <c0V2Aainfix =c0V0Oainfix <c0V0F">
...@@ -248,7 +248,7 @@ ...@@ -248,7 +248,7 @@
locfile="../algo64.mlw" locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19" loclnum="37" loccnumb="10" loccnume="19"
expl="10. postcondition" expl="10. postcondition"
sum="ae131e9ba218ef49491fed41ba2b7dda" sum="43d862bf6f497828c73c4712edee4a92"
proved="true" proved="true"
expanded="true" expanded="true"
shape="postconditionapermut_subV1V1V2ainfix +V3c1INainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F"> shape="postconditionapermut_subV1V1V2ainfix +V3c1INainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F">
...@@ -268,7 +268,7 @@ ...@@ -268,7 +268,7 @@
locfile="../algo64.mlw" locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19" loclnum="37" loccnumb="10" loccnume="19"
expl="11. postcondition" expl="11. postcondition"
sum="7d85e987becf04086d6bca226dae8830" sum="6a5a66d91b9141edeb86e53fbf63fd1b"
proved="true" proved="true"
expanded="true" expanded="true"
shape="postconditionasorted_subV1V2ainfix +V3c1INainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F"> shape="postconditionasorted_subV1V2ainfix +V3c1INainfix <V2V3Iainfix <V3V0Aainfix <=V2V3Aainfix <=c0V2Aainfix <=c0V0F">
......
This diff is collapsed.
...@@ -43,7 +43,7 @@ ...@@ -43,7 +43,7 @@
name="Test" name="Test"
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="76" loccnumb="7" loccnume="11" loclnum="76" loccnumb="7" loccnume="11"
sum="39ecdf8d4131f1fa5ea55567c3113653" sum="49f1d59ec96a8354b1d5ebdb335c5d91"
proved="true" proved="true"
expanded="false" expanded="false"
shape="ainfix <=aprefix -aposition_valueado_moveV0V1aminmaxV0c1IamemV1V2Lalegal_movesV0F"> shape="ainfix <=aprefix -aposition_valueado_moveV0V1aminmaxV0c1IamemV1V2Lalegal_movesV0F">
...@@ -77,7 +77,7 @@ ...@@ -77,7 +77,7 @@
name="minmax_bound" name="minmax_bound"
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="82" loccnumb="8" loccnume="20" loclnum="82" loccnumb="8" loccnume="20"
sum="4ca2330e7b982f5e5220247841678ce2" sum="36f935fa5bef1fa57c466f78bf342ee7"
proved="true" proved="true"
expanded="false" expanded="false"
shape="ainfix <aminmaxV0V1ainfinityAainfix <aprefix -ainfinityaminmaxV0V1Iainfix >=V1c0F"> shape="ainfix <aminmaxV0V1ainfinityAainfix <aprefix -ainfinityaminmaxV0V1Iainfix >=V1c0F">
...@@ -95,7 +95,7 @@ ...@@ -95,7 +95,7 @@
name="minmax_nomove" name="minmax_nomove"
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="86" loccnumb="8" loccnume="21" loclnum="86" loccnumb="8" loccnume="21"
sum="3444932eae1400ed3e48ac2b0bc42789" sum="50c6f41696a65d12df47d1e67f624e61"
proved="true" proved="true"
expanded="false" expanded="false"
shape="ainfix =aminmaxV0V1aposition_valueV0Iainfix =alegal_movesV0aNilAainfix >=V1c0F"> shape="ainfix =aminmaxV0V1aposition_valueV0Iainfix =alegal_movesV0aNilAainfix >=V1c0F">
...@@ -160,7 +160,7 @@ ...@@ -160,7 +160,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="109" loccnumb="10" loccnume="31" loclnum="109" loccnumb="10" loccnume="31"
expl="VC for move_value_alpha_beta" expl="VC for move_value_alpha_beta"
sum="9c16850c7c4432bf01f71e065f85eada" sum="c8b58a3c3bbe07a23869dfdc34af9968"
proved="true" proved="true"
expanded="false" expanded="false"
shape="iiainfix <=V10V0ainfix >=V10V1ainfix <=V11aprefix -V1ainfix =V10aprefix -V11ainfix <V11aprefix -V0Aainfix <aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix >=V9V7ainfix <=V9V8ainfix <=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix <aminmaxV5V6V7Aainfix <V8aminmaxV5V6FAainfix >=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix >=V3c1F"> shape="iiainfix <=V10V0ainfix >=V10V1ainfix <=V11aprefix -V1ainfix =V10aprefix -V11ainfix <V11aprefix -V0Aainfix <aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix >=V9V7ainfix <=V9V8ainfix <=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix <aminmaxV5V6V7Aainfix <V8aminmaxV5V6FAainfix >=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix >=V3c1F">
...@@ -175,7 +175,7 @@ ...@@ -175,7 +175,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="109" loccnumb="10" loccnume="31" loclnum="109" loccnumb="10" loccnume="31"
expl="1. precondition" expl="1. precondition"
sum="55761e4663efa8c6079c6e5b0f82c442" sum="c275ced31a1fa2d12b72239c445ef1e4"
proved="true" proved="true"
expanded="false" expanded="false"
shape="preconditionainfix >=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix >=V3c1F"> shape="preconditionainfix >=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix >=V3c1F">
...@@ -235,7 +235,7 @@ ...@@ -235,7 +235,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="109" loccnumb="10" loccnume="31" loclnum="109" loccnumb="10" loccnume="31"
expl="2. postcondition" expl="2. postcondition"
sum="85cd410b72ab2d173ce5ce532fbf9ea6" sum="dd2ab53bbe91c0770db92e5ce9b73d35"
proved="true" proved="true"
expanded="false" expanded="false"
shape="postconditioniiainfix <=V10V0ainfix >=V10V1ainfix <=V11aprefix -V1ainfix =V10aprefix -V11ainfix <V11aprefix -V0Aainfix <aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix >=V9V7ainfix <=V9V8ainfix <=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix <aminmaxV5V6V7Aainfix <V8aminmaxV5V6FIainfix >=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix >=V3c1F"> shape="postconditioniiainfix <=V10V0ainfix >=V10V1ainfix <=V11aprefix -V1ainfix =V10aprefix -V11ainfix <V11aprefix -V0Aainfix <aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix >=V9V7ainfix <=V9V8ainfix <=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix <aminmaxV5V6V7Aainfix <V8aminmaxV5V6FIainfix >=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix >=V3c1F">
...@@ -250,7 +250,7 @@ ...@@ -250,7 +250,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="109" loccnumb="10" loccnume="31" loclnum="109" loccnumb="10" loccnume="31"
expl="1. postcondition" expl="1. postcondition"
sum="501826e08ad0bf90a8de8152493aa5c7" sum="7afd272bfdaa453759492f00b6f351c2"
proved="true" proved="true"
expanded="false" expanded="false"
shape="postconditionainfix =V10aprefix -V11Iainfix <V11aprefix -V0Aainfix <aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix >=V9V7ainfix <=V9V8ainfix <=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix <aminmaxV5V6V7Aainfix <V8aminmaxV5V6FIainfix >=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix >=V3c1F"> shape="postconditionainfix =V10aprefix -V11Iainfix <V11aprefix -V0Aainfix <aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix >=V9V7ainfix <=V9V8ainfix <=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix <aminmaxV5V6V7Aainfix <V8aminmaxV5V6FIainfix >=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix >=V3c1F">
...@@ -270,7 +270,7 @@ ...@@ -270,7 +270,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="109" loccnumb="10" loccnume="31" loclnum="109" loccnumb="10" loccnume="31"
expl="2. postcondition" expl="2. postcondition"
sum="25e9961b18f4823768f425ccde9100c0" sum="9968d2e69f7dfeedb4d0ffddb8350051"
proved="true" proved="true"
expanded="false" expanded="false"
shape="postconditionainfix >=V10V1Iainfix <=V11aprefix -V1INainfix <V11aprefix -V0Aainfix <aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix >=V9V7ainfix <=V9V8ainfix <=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix <aminmaxV5V6V7Aainfix <V8aminmaxV5V6FIainfix >=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix >=V3c1F"> shape="postconditionainfix >=V10V1Iainfix <=V11aprefix -V1INainfix <V11aprefix -V0Aainfix <aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix >=V9V7ainfix <=V9V8ainfix <=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix <aminmaxV5V6V7Aainfix <V8aminmaxV5V6FIainfix >=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix >=V3c1F">
...@@ -290,7 +290,7 @@ ...@@ -290,7 +290,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="109" loccnumb="10" loccnume="31" loclnum="109" loccnumb="10" loccnume="31"
expl="3. postcondition" expl="3. postcondition"
sum="f44085fb23f77a7996b73acc2ca13982" sum="aa93a0eccb2482e65c9a6570a54f1e6e"
proved="true" proved="true"
expanded="false" expanded="false"
shape="postconditionainfix <=V10V0INainfix <=V11aprefix -V1INainfix <V11aprefix -V0Aainfix <aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix >=V9V7ainfix <=V9V8ainfix <=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix <aminmaxV5V6V7Aainfix <V8aminmaxV5V6FIainfix >=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix >=V3c1F"> shape="postconditionainfix <=V10V0INainfix <=V11aprefix -V1INainfix <V11aprefix -V0Aainfix <aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix >=V9V7ainfix <=V9V8ainfix <=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix <aminmaxV5V6V7Aainfix <V8aminmaxV5V6FIainfix >=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix >=V3c1F">
...@@ -314,7 +314,7 @@ ...@@ -314,7 +314,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15" loclnum="121" loccnumb="7" loccnume="15"
expl="VC for negabeta" expl="VC for negabeta"
sum="0f02503975b959414e121bd7d48cd6bc" sum="05a77d1efc956b485ea88372111769ed"
proved="false" proved="false"
expanded="true" expanded="true"
shape="iCiiainfix >=V4V1ainfix <=V4V0ainfix <=aminmaxV2V3V0ainfix =V4aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2aNiliiiainfix >=V9V1ainfix <=V9V0ainfix <=aminmaxV2V3V0ainfix =V9aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Iiiiainfix >=V9V1ainfix <=V9V8ainfix <=V11V8ainfix =V9V11ainfix <V11V1Aainfix <V8V11LaminaTuple2V2V3V10ainfix =V9V7ais_emptyV10LaelementsV6FAainfix >=V3c1LamaxV7V0iiainfix >=V7V1ainfix <=V7V0ainfix <=aminmaxV2V3V0ainfix =V7aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3ainfix >=V7V1Iiiainfix <=V7V0ainfix >=V7V1ainfix <=V12aprefix -V1ainfix =V7aprefix -V12ainfix <V12aprefix -V0Aainfix <aprefix -V1V12Laminmaxado_moveV2V5ainfix -V3c1FAainfix >=V3c1aConsVValegal_movesV2iiainfix >=V13V1ainfix <=V13V0ainfix <=aminmaxV2V3V0ainfix =V13aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2ainfix =V3c0Iainfix >=V3c0F"> shape="iCiiainfix >=V4V1ainfix <=V4V0ainfix <=aminmaxV2V3V0ainfix =V4aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2aNiliiiainfix >=V9V1ainfix <=V9V0ainfix <=aminmaxV2V3V0ainfix =V9aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Iiiiainfix >=V9V1ainfix <=V9V8ainfix <=V11V8ainfix =V9V11ainfix <V11V1Aainfix <V8V11LaminaTuple2V2V3V10ainfix =V9V7ais_emptyV10LaelementsV6FAainfix >=V3c1LamaxV7V0iiainfix >=V7V1ainfix <=V7V0ainfix <=aminmaxV2V3V0ainfix =V7aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3ainfix >=V7V1Iiiainfix <=V7V0ainfix >=V7V1ainfix <=V12aprefix -V1ainfix =V7aprefix -V12ainfix <V12aprefix -V0Aainfix <aprefix -V1V12Laminmaxado_moveV2V5ainfix -V3c1FAainfix >=V3c1aConsVValegal_movesV2iiainfix >=V13V1ainfix <=V13V0ainfix <=aminmaxV2V3V0ainfix =V13aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2ainfix =V3c0Iainfix >=V3c0F">
...@@ -329,7 +329,7 @@ ...@@ -329,7 +329,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15" loclnum="121" loccnumb="7" loccnume="15"
expl="1. postcondition" expl="1. postcondition"
sum="cf2918982e1fd0da3d21ab800ab3769c" sum="27f597ad07473cad2eb0faa91ef4c187"
proved="true" proved="true"
expanded="false" expanded="false"
shape="postconditioniiainfix >=V4V1ainfix <=V4V0ainfix <=aminmaxV2V3V0ainfix =V4aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2Iainfix =V3c0Iainfix >=V3c0F"> shape="postconditioniiainfix >=V4V1ainfix <=V4V0ainfix <=aminmaxV2V3V0ainfix =V4aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2Iainfix =V3c0Iainfix >=V3c0F">
...@@ -352,7 +352,7 @@ ...@@ -352,7 +352,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15" loclnum="121" loccnumb="7" loccnume="15"
expl="1. postcondition" expl="1. postcondition"
sum="c77b47571862f67ba3a3bf8be3ac1eb6" sum="ecd8adfd7126841791e6a54a6fb3b287"
proved="true" proved="true"
expanded="false" expanded="false"
shape="postconditionainfix =V4aminmaxV2V3Iainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2Iainfix =V3c0Iainfix >=V3c0F"> shape="postconditionainfix =V4aminmaxV2V3Iainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2Iainfix =V3c0Iainfix >=V3c0F">
...@@ -380,7 +380,7 @@ ...@@ -380,7 +380,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15" loclnum="121" loccnumb="7" loccnume="15"
expl="2. postcondition" expl="2. postcondition"
sum="c82588ea72ee8ad05fe91f5c2e0e5746" sum="4677ff1dc8fbd2439b4da3e20ebdc830"
proved="true" proved="true"
expanded="false" expanded="false"
shape="postconditionainfix <=V4V0Iainfix <=aminmaxV2V3V0INainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2Iainfix =V3c0Iainfix >=V3c0F"> shape="postconditionainfix <=V4V0Iainfix <=aminmaxV2V3V0INainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2Iainfix =V3c0Iainfix >=V3c0F">
...@@ -408,7 +408,7 @@ ...@@ -408,7 +408,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15" loclnum="121" loccnumb="7" loccnume="15"
expl="3. postcondition" expl="3. postcondition"
sum="ac41aafadb86686129e1f113e0e342da" sum="8aad6498b015efdd20afc1763dce71f6"
proved="true" proved="true"
expanded="false" expanded="false"
shape="postconditionainfix >=V4V1INainfix <=aminmaxV2V3V0INainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2Iainfix =V3c0Iainfix >=V3c0F"> shape="postconditionainfix >=V4V1INainfix <=aminmaxV2V3V0INainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2Iainfix =V3c0Iainfix >=V3c0F">
...@@ -438,7 +438,7 @@ ...@@ -438,7 +438,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15" loclnum="121" loccnumb="7" loccnume="15"
expl="2. postcondition" expl="2. postcondition"
sum="422d115091d3b137ad77bd653a4f29d2" sum="6e47a941f553fd3587122c973259e083"
proved="true" proved="true"
expanded="false" expanded="false"
shape="postconditionCiiainfix >=V4V1ainfix <=V4V0ainfix <=aminmaxV2V3V0ainfix =V4aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2aNiltaConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F"> shape="postconditionCiiainfix >=V4V1ainfix <=V4V0ainfix <=aminmaxV2V3V0ainfix =V4aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2aNiltaConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F">
...@@ -453,7 +453,7 @@ ...@@ -453,7 +453,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15" loclnum="121" loccnumb="7" loccnume="15"
expl="1. postcondition" expl="1. postcondition"
sum="23981ddcfb3dbcf1b27030d385ac6a5e" sum="5d51b4c8073344de3015ded4d7176f83"
proved="true" proved="true"
expanded="false" expanded="false"
shape="postconditionCainfix =V4aminmaxV2V3Iainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2aNiltaConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F"> shape="postconditionCainfix =V4aminmaxV2V3Iainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2aNiltaConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F">
...@@ -489,7 +489,7 @@ ...@@ -489,7 +489,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15" loclnum="121" loccnumb="7" loccnume="15"
expl="2. postcondition" expl="2. postcondition"
sum="c1dd4b7d2d32be35b463fd55a887a245" sum="33a1dc2e73dbc9df2cb6b42bbd703d38"
proved="true" proved="true"
expanded="false" expanded="false"
shape="postconditionCainfix <=V4V0Iainfix <=aminmaxV2V3V0INainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2aNiltaConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F"> shape="postconditionCainfix <=V4V0Iainfix <=aminmaxV2V3V0INainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2aNiltaConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F">
...@@ -525,7 +525,7 @@ ...@@ -525,7 +525,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15" loclnum="121" loccnumb="7" loccnume="15"
expl="3. postcondition" expl="3. postcondition"
sum="4abac57c327bebc6b2697bc6ab5c9ed2" sum="912aaf5fe713dacaa23f8f4a376af823"
proved="true" proved="true"
expanded="false" expanded="false"
shape="postconditionCainfix >=V4V1INainfix <=aminmaxV2V3V0INainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2aNiltaConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F"> shape="postconditionCainfix >=V4V1INainfix <=aminmaxV2V3V0INainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Laposition_valueV2aNiltaConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F">
...@@ -563,7 +563,7 @@ ...@@ -563,7 +563,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15" loclnum="121" loccnumb="7" loccnume="15"
expl="3. precondition" expl="3. precondition"
sum="0c6e21b2f13cd5beeef2d87ae4c49cbe" sum="1e2508fe555c0a2be5855858f07a622e"
proved="true" proved="true"
expanded="false" expanded="false"
shape="preconditionCtaNilainfix >=V3c1aConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F"> shape="preconditionCtaNilainfix >=V3c1aConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F">
...@@ -599,7 +599,7 @@ ...@@ -599,7 +599,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15" loclnum="121" loccnumb="7" loccnume="15"
expl="4. postcondition" expl="4. postcondition"
sum="b512ffd5edfb343b2efff3903fe980f1" sum="a478ae87a32317512fd49c42471d49a9"
proved="false" proved="false"
expanded="true" expanded="true"
shape="postconditionCtaNiliiainfix >=V6V1ainfix <=V6V0ainfix <=aminmaxV2V3V0ainfix =V6aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Iainfix >=V6V1Iiiainfix <=V6V0ainfix >=V6V1ainfix <=V7aprefix -V1ainfix =V6aprefix -V7ainfix <V7aprefix -V0Aainfix <aprefix -V1V7Laminmaxado_moveV2V4ainfix -V3c1FIainfix >=V3c1aConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F"> shape="postconditionCtaNiliiainfix >=V6V1ainfix <=V6V0ainfix <=aminmaxV2V3V0ainfix =V6aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Iainfix >=V6V1Iiiainfix <=V6V0ainfix >=V6V1ainfix <=V7aprefix -V1ainfix =V6aprefix -V7ainfix <V7aprefix -V0Aainfix <aprefix -V1V7Laminmaxado_moveV2V4ainfix -V3c1FIainfix >=V3c1aConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F">
...@@ -611,7 +611,7 @@ ...@@ -611,7 +611,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15" loclnum="121" loccnumb="7" loccnume="15"
expl="5. precondition" expl="5. precondition"
sum="30af0bc4221efe452586c70f18a1b51b" sum="3fa8dfeb7d68ed69b5fc21428f2ab0a3"
proved="true" proved="true"
expanded="false" expanded="false"
shape="preconditionCtaNilainfix >=V3c1LamaxV6V0INainfix >=V6V1Iiiainfix <=V6V0ainfix >=V6V1ainfix <=V8aprefix -V1ainfix =V6aprefix -V8ainfix <V8aprefix -V0Aainfix <aprefix -V1V8Laminmaxado_moveV2V4ainfix -V3c1FIainfix >=V3c1aConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F"> shape="preconditionCtaNilainfix >=V3c1LamaxV6V0INainfix >=V6V1Iiiainfix <=V6V0ainfix >=V6V1ainfix <=V8aprefix -V1ainfix =V6aprefix -V8ainfix <V8aprefix -V0Aainfix <aprefix -V1V8Laminmaxado_moveV2V4ainfix -V3c1FIainfix >=V3c1aConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F">
...@@ -647,7 +647,7 @@ ...@@ -647,7 +647,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15" loclnum="121" loccnumb="7" loccnume="15"
expl="6. postcondition" expl="6. postcondition"
sum="f79bb52db7c0913f4261c65c2305566f" sum="ddb265720958a56e64141edf4b668568"
proved="false" proved="false"
expanded="true" expanded="true"
shape="postconditionCtaNiliiainfix >=V8V1ainfix <=V8V0ainfix <=aminmaxV2V3V0ainfix =V8aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Iiiiainfix >=V8V1ainfix <=V8V7ainfix <=V10V7ainfix =V8V10ainfix <V10V1Aainfix <V7V10LaminaTuple2V2V3V9ainfix =V8V6ais_emptyV9LaelementsV5FIainfix >=V3c1LamaxV6V0INainfix >=V6V1Iiiainfix <=V6V0ainfix >=V6V1ainfix <=V11aprefix -V1ainfix =V6aprefix -V11ainfix <V11aprefix -V0Aainfix <aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1FIainfix >=V3c1aConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F"> shape="postconditionCtaNiliiainfix >=V8V1ainfix <=V8V0ainfix <=aminmaxV2V3V0ainfix =V8aminmaxV2V3ainfix <aminmaxV2V3V1Aainfix <V0aminmaxV2V3Iiiiainfix >=V8V1ainfix <=V8V7ainfix <=V10V7ainfix =V8V10ainfix <V10V1Aainfix <V7V10LaminaTuple2V2V3V9ainfix =V8V6ais_emptyV9LaelementsV5FIainfix >=V3c1LamaxV6V0INainfix >=V6V1Iiiainfix <=V6V0ainfix >=V6V1ainfix <=V11aprefix -V1ainfix =V6aprefix -V11ainfix <V11aprefix -V0Aainfix <aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1FIainfix >=V3c1aConsVValegal_movesV2INainfix =V3c0Iainfix >=V3c0F">
...@@ -661,7 +661,7 @@ ...@@ -661,7 +661,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="139" loccnumb="7" loccnume="19" loclnum="139" loccnumb="7" loccnume="19"
expl="VC for negabeta_rec" expl="VC for negabeta_rec"
sum="d704ecc1238833f8c3f97ca20ec9fb99" sum="3c01b422e41c927944241e40b60d6ef8"
proved="false" proved="false"
expanded="true" expanded="true"
shape="Ciiainfix >=V4V1ainfix <=V4V0ainfix <=V7V0ainfix =V4V7ainfix <V7V1Aainfix <V0V7LaminaTuple2V2V3V6INais_emptyV6LaelementsV5aNiliiiiainfix >=V13V1ainfix <=V13V0ainfix <=V15V0ainfix =V13V15ainfix <V15V1Aainfix <V0V15LaminaTuple2V2V3V14ainfix =V13V4ais_emptyV14LaelementsV5Iiiiainfix >=V13V1ainfix <=V13V12ainfix <=V17V12ainfix =V13V17ainfix <V17V1Aainfix <V12V17LaminaTuple2V2V3V16ainfix =V13V11ais_emptyV16LaelementsV9FAainfix >=V3c1LamaxV11V0iiiainfix >=V11V1ainfix <=V11V0ainfix <=V19V0ainfix =V11V19ainfix <V19V1Aainfix <V0V19LaminaTuple2V2V3V18ainfix =V11V4ais_emptyV18LaelementsV5ainfix >=V11V1LamaxV10V4Iiiainfix <=V10V0ainfix >=V10V1ainfix <=V20aprefix -V1ainfix =V10aprefix -V20ainfix <V20aprefix -V0Aainfix <aprefix -V1V20Laminmaxado_moveV2V8ainfix -V3c1FAainfix >=V3c1aConsVVV5Iainfix >=V3c1F"> shape="Ciiainfix >=V4V1ainfix <=V4V0ainfix <=V7V0ainfix =V4V7ainfix <V7V1Aainfix <V0V7LaminaTuple2V2V3V6INais_emptyV6LaelementsV5aNiliiiiainfix >=V13V1ainfix <=V13V0ainfix <=V15V0ainfix =V13V15ainfix <V15V1Aainfix <V0V15LaminaTuple2V2V3V14ainfix =V13V4ais_emptyV14LaelementsV5Iiiiainfix >=V13V1ainfix <=V13V12ainfix <=V17V12ainfix =V13V17ainfix <V17V1Aainfix <V12V17LaminaTuple2V2V3V16ainfix =V13V11ais_emptyV16LaelementsV9FAainfix >=V3c1LamaxV11V0iiiainfix >=V11V1ainfix <=V11V0ainfix <=V19V0ainfix =V11V19ainfix <V19V1Aainfix <V0V19LaminaTuple2V2V3V18ainfix =V11V4ais_emptyV18LaelementsV5ainfix >=V11V1LamaxV10V4Iiiainfix <=V10V0ainfix >=V10V1ainfix <=V20aprefix -V1ainfix =V10aprefix -V20ainfix <V20aprefix -V0Aainfix <aprefix -V1V20Laminmaxado_moveV2V8ainfix -V3c1FAainfix >=V3c1aConsVVV5Iainfix >=V3c1F">
...@@ -676,7 +676,7 @@ ...@@ -676,7 +676,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="139" loccnumb="7" loccnume="19" loclnum="139" loccnumb="7" loccnume="19"
expl="1. postcondition" expl="1. postcondition"
sum="7441d365c8d6583fc608c6b96c48eb1c" sum="8229d2728dea6754f8225411da822e26"
proved="true" proved="true"
expanded="false" expanded="false"
shape="postconditionCiiainfix >=V4V1ainfix <=V4V0ainfix <=V7V0ainfix =V4V7ainfix <V7V1Aainfix <V0V7LaminaTuple2V2V3V6INais_emptyV6LaelementsV5aNiltaConsVVV5Iainfix >=V3c1F"> shape="postconditionCiiainfix >=V4V1ainfix <=V4V0ainfix <=V7V0ainfix =V4V7ainfix <V7V1Aainfix <V0V7LaminaTuple2V2V3V6INais_emptyV6LaelementsV5aNiltaConsVVV5Iainfix >=V3c1F">
...@@ -696,7 +696,7 @@ ...@@ -696,7 +696,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="139" loccnumb="7" loccnume="19" loclnum="139" loccnumb="7" loccnume="19"
expl="2. precondition" expl="2. precondition"
sum="a6233c6593c2c83c63422cd896d89ba6" sum="f82fa5f417a96d337ce2efae7248b1e8"
proved="true" proved="true"
expanded="false" expanded="false"
shape="preconditionCtaNilainfix >=V3c1aConsVVV5Iainfix >=V3c1F"> shape="preconditionCtaNilainfix >=V3c1aConsVVV5Iainfix >=V3c1F">
...@@ -716,7 +716,7 @@ ...@@ -716,7 +716,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="139" loccnumb="7" loccnume="19" loclnum="139" loccnumb="7" loccnume="19"
expl="3. postcondition" expl="3. postcondition"
sum="0771cea9ac02451844196bcc37ebb460" sum="fd64a61bcbe77a9d9fddd02f3e69a20a"
proved="false" proved="false"
expanded="true" expanded="true"
shape="postconditionCtaNiliiiainfix >=V9V1ainfix <=V9V0ainfix <=V11V0ainfix =V9V11ainfix <V11V1Aainfix <V0V11LaminaTuple2V2V3V10ainfix =V9V4ais_emptyV10LaelementsV5Iainfix >=V9V1LamaxV8V4Iiiainfix <=V8V0ainfix >=V8V1ainfix <=V12aprefix -V1ainfix =V8aprefix -V12ainfix <V12aprefix -V0Aainfix <aprefix -V1V12Laminmaxado_moveV2V6ainfix -V3c1FIainfix >=V3c1aConsVVV5Iainfix >=V3c1F"> shape="postconditionCtaNiliiiainfix >=V9V1ainfix <=V9V0ainfix <=V11V0ainfix =V9V11ainfix <V11V1Aainfix <V0V11LaminaTuple2V2V3V10ainfix =V9V4ais_emptyV10LaelementsV5Iainfix >=V9V1LamaxV8V4Iiiainfix <=V8V0ainfix >=V8V1ainfix <=V12aprefix -V1ainfix =V8aprefix -V12ainfix <V12aprefix -V0Aainfix <aprefix -V1V12Laminmaxado_moveV2V6ainfix -V3c1FIainfix >=V3c1aConsVVV5Iainfix >=V3c1F">
...@@ -728,7 +728,7 @@ ...@@ -728,7 +728,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="139" loccnumb="7" loccnume="19" loclnum="139" loccnumb="7" loccnume="19"
expl="4. precondition" expl="4. precondition"
sum="64958f8c3f917462994213438324d9bc" sum="636222815d93b2f0e0548a577957a987"
proved="true" proved="true"
expanded="false" expanded="false"
shape="preconditionCtaNilainfix >=V3c1LamaxV9V0INainfix >=V9V1LamaxV8V4Iiiainfix <=V8V0ainfix >=V8V1ainfix <=V11aprefix -V1ainfix =V8aprefix -V11ainfix <V11aprefix -V0Aainfix <aprefix -V1V11Laminmaxado_moveV2V6ainfix -V3c1FIainfix >=V3c1aConsVVV5Iainfix >=V3c1F"> shape="preconditionCtaNilainfix >=V3c1LamaxV9V0INainfix >=V9V1LamaxV8V4Iiiainfix <=V8V0ainfix >=V8V1ainfix <=V11aprefix -V1ainfix =V8aprefix -V11ainfix <V11aprefix -V0Aainfix <aprefix -V1V11Laminmaxado_moveV2V6ainfix -V3c1FIainfix >=V3c1aConsVVV5Iainfix >=V3c1F">
...@@ -748,7 +748,7 @@ ...@@ -748,7 +748,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="139" loccnumb="7" loccnume="19" loclnum="139" loccnumb="7" loccnume="19"
expl="5. postcondition" expl="5. postcondition"
sum="6413449d94f75526fa40d1b592ec6b9e" sum="d01dbe371a33acafd690a65a8ca71394"
proved="false" proved="false"
expanded="true" expanded="true"
shape="postconditionCtaNiliiiainfix >=V11V1ainfix <=V11V0ainfix <=V13V0ainfix =V11V13ainfix <V13V1Aainfix <V0V13LaminaTuple2V2V3V12ainfix =V11V4ais_emptyV12LaelementsV5Iiiiainfix >=V11V1ainfix <=V11V10ainfix <=V15V10ainfix =V11V15ainfix <V15V1Aainfix <V10V15LaminaTuple2V2V3V14ainfix =V11V9ais_emptyV14LaelementsV7FIainfix >=V3c1LamaxV9V0INainfix >=V9V1LamaxV8V4Iiiainfix <=V8V0ainfix >=V8V1ainfix <=V16aprefix -V1ainfix =V8aprefix -V16ainfix <V16aprefix -V0Aainfix <aprefix -V1V16Laminmaxado_moveV2V6ainfix -V3c1FIainfix >=V3c1aConsVVV5Iainfix >=V3c1F"> shape="postconditionCtaNiliiiainfix >=V11V1ainfix <=V11V0ainfix <=V13V0ainfix =V11V13ainfix <V13V1Aainfix <V0V13LaminaTuple2V2V3V12ainfix =V11V4ais_emptyV12LaelementsV5Iiiiainfix >=V11V1ainfix <=V11V10ainfix <=V15V10ainfix =V11V15ainfix <V15V1Aainfix <V10V15LaminaTuple2V2V3V14ainfix =V11V9ais_emptyV14LaelementsV7FIainfix >=V3c1LamaxV9V0INainfix >=V9V1LamaxV8V4Iiiainfix <=V8V0ainfix >=V8V1ainfix <=V16aprefix -V1ainfix =V8aprefix -V16ainfix <V16aprefix -V0Aainfix <aprefix -V1V16Laminmaxado_moveV2V6ainfix -V3c1FIainfix >=V3c1aConsVVV5Iainfix >=V3c1F">
...@@ -762,7 +762,7 @@ ...@@ -762,7 +762,7 @@
locfile="../alphaBeta.mlw" locfile="../alphaBeta.mlw"
loclnum="161" loccnumb="4" loccnume="14" loclnum="161" loccnumb="4" loccnume="14"
expl="VC for alpha_beta" expl="VC for alpha_beta"
sum="156a59bced97bf15c4091f9772c7a8d8" sum="fd23aae1d6199ad7c07aaad267561898"
proved="true" proved="true"
expanded="false" expanded="false"
shape="ainfix =V4aminmaxV0V1Iiiainfix >=V4V2ainfix <=V4V3ainfix <=aminmaxV0V1V3ainfix =V4aminmaxV0V1ainfix <aminmaxV0V1V2Aainfix <V3aminmaxV0V1FAainfix >=V1c0Laprefix -ainfinityLainfinityIainfix >=V1c0F"> shape="ainfix =V4aminmaxV0V1Iiiainfix >=V4V2ainfix <=V4V3ainfix <=aminmaxV0V1V3ainfix =V4aminmaxV0V1ainfix <aminmaxV0V1V2Aainfix <V3aminmaxV0V1FAainfix >=V1c0Laprefix -ainfinityLainfinityIainfix >=V1c0F">
......
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
locfile="../arm.mlw" locfile="../arm.mlw"
loclnum="16" loccnumb="6" loccnume="20" loclnum="16" loccnumb="6" loccnume="20"
expl="VC for insertion_sort" expl="VC for insertion_sort"
sum="0253f804b94902a25f1e77e1d4c459c1" sum="7a48ddec008b758b68d1b8f7bf242745"
proved="false" proved="false"
expanded="false" expanded="false"
shape="iainfix <=V6c45Aainfix =V7c9Aainfix <=c0V0iainfix <ainfix -c10V16ainfix -c10V5Aainfix <=c0ainfix -c10V5Aainfix <=ainfix *c2V12ainfix *ainfix -V16c2ainfix -V16c1Aainfix =V10ainfix -V16c2AainvV14Aainfix <=V16c11Aainfix <=c2V16Iainfix =V16ainfix +V5c1Fainfix <V22V11Aainfix <=c0V11Aainfix <=ainfix *c2V17ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V22Aainvamk arrayV0V21Aainfix <=V22V5Aainfix <=c1V22Iainfix =V22ainfix -V11c1FIainfix =V21asetV19V20agetV13V11Aainfix <=c0V0FAainfix <V20V0Aainfix <=c0V20Lainfix -V11c1Iainfix =V19asetV13V11agetV13V18Aainfix <=c0V0FAainfix <V11V0Aainfix <=c0V11Aainfix <V18V0Aainfix <=c0V18Lainfix -V11c1Aainfix <V11V0Aainfix <=c0V11Iainfix =V17ainfix +V12c1Fainfix <agetV13V11agetV13V15Aainfix <V11V0Aainfix <=c0V11Aainfix <V15V0Aainfix <=c0V15Aainfix <=c0V0Lainfix -V11c1Iainfix <=ainfix *c2V12ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V11AainvV14Aainfix <=V11V5Aainfix <=c1V11Lamk arrayV0V13FAainfix <=ainfix *c2V6ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V5AainvV9Aainfix <=V5V5Aainfix <=c1V5Iainfix =V10ainfix +V7c1Fainfix <=V5c10Iainfix <=ainfix *c2V6ainfix *ainfix -V5c2ainfix -V5c1Aainfix =V7ainfix -V5c2AainvV9Aainfix <=V5c11Aainfix <=c2V5Lamk arrayV0V8FAainfix <=ainfix *c2V1ainfix *ainfix -c2c2ainfix -c2c1Aainfix =V2ainfix -c2c2AainvV4Aainfix <=c2c11Aainfix <=c2c2Iainfix =V1c0Aainfix =V2c0AainvV4Aainfix <=c0V0Lamk arrayV0V3FF"> shape="iainfix <=V6c45Aainfix =V7c9Aainfix <=c0V0iainfix <ainfix -c10V16ainfix -c10V5Aainfix <=c0ainfix -c10V5Aainfix <=ainfix *c2V12ainfix *ainfix -V16c2ainfix -V16c1Aainfix =V10ainfix -V16c2AainvV14Aainfix <=V16c11Aainfix <=c2V16Iainfix =V16ainfix +V5c1Fainfix <V22V11Aainfix <=c0V11Aainfix <=ainfix *c2V17ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V22Aainvamk arrayV0V21Aainfix <=V22V5Aainfix <=c1V22Iainfix =V22ainfix -V11c1FIainfix =V21asetV19V20agetV13V11Aainfix <=c0V0FAainfix <V20V0Aainfix <=c0V20Lainfix -V11c1Iainfix =V19asetV13V11agetV13V18Aainfix <=c0V0FAainfix <V11V0Aainfix <=c0V11Aainfix <V18V0Aainfix <=c0V18Lainfix -V11c1Aainfix <V11V0Aainfix <=c0V11Iainfix =V17ainfix +V12c1Fainfix <agetV13V11agetV13V15Aainfix <V11V0Aainfix <=c0V11Aainfix <V15V0Aainfix <=c0V15Aainfix <=c0V0Lainfix -V11c1Iainfix <=ainfix *c2V12ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V11AainvV14Aainfix <=V11V5Aainfix <=c1V11Lamk arrayV0V13FAainfix <=ainfix *c2V6ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V5AainvV9Aainfix <=V5V5Aainfix <=c1V5Iainfix =V10ainfix +V7c1Fainfix <=V5c10Iainfix <=ainfix *c2V6ainfix *ainfix -V5c2ainfix -V5c1Aainfix =V7ainfix -V5c2AainvV9Aainfix <=V5c11Aainfix <=c2V5Lamk arrayV0V8FAainfix <=ainfix *c2V1ainfix *ainfix -c2c2ainfix -c2c1Aainfix =V2ainfix -c2c2AainvV4Aainfix <=c2c11Aainfix <=c2c2Iainfix =V1c0Aainfix =V2c0AainvV4Aainfix <=c0V0Lamk arrayV0V3FF">
...@@ -50,7 +50,7 @@ ...@@ -50,7 +50,7 @@
locfile="../arm.mlw" locfile="../arm.mlw"
loclnum="120" loccnumb="6" loccnume="18" loclnum="120" loccnumb="6" loccnume="18"
expl="VC for path_init_l2" expl="VC for path_init_l2"
sum="beb23c3645199bfd98a3ca8ba1a81b49" sum="b7f073634088aae7b5aaf2b40c15baf4"
proved="true" proved="true"
expanded="true" expanded="true"