Commit 9bf1998f authored by Andrei Paskevich's avatar Andrei Paskevich

update sessions (in progress)

parent ac976a84
...@@ -11,8 +11,12 @@ ...@@ -11,8 +11,12 @@
version="2.4.1"/> version="2.4.1"/>
<prover <prover
id="2" id="2"
name="Spass" name="Eprover"
version="3.7"/> version="1.6"/>
<prover
id="3"
name="Vampire"
version="0.6"/>
<file <file
name="../algo63.mlw" name="../algo63.mlw"
verified="true" verified="true"
...@@ -28,9 +32,9 @@ ...@@ -28,9 +32,9 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="23" loccnumb="6" loccnume="14" loclnum="23" loccnumb="6" loccnume="14"
expl="VC for exchange" expl="VC for exchange"
sum="863d335d0c938d951df3f228ee666db7" sum="3e44f4783367234e4abc31b0d08c3493"
proved="true" proved="true"
expanded="true" expanded="false"
shape="apermut_subV5V7V1ainfix +V2c1AaexchangeV5V7V3V4Iainfix =V7asetV6V4agetV5V3Aainfix &lt;=c0V0FAainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix =V6asetV5V3agetV5V4Aainfix &lt;=c0V0FAainfix &lt;V3V0Aainfix &lt;=c0V3Aainfix &lt;V4V0Aainfix &lt;=c0V4Aainfix &lt;V3V0Aainfix &lt;=c0V3Iainfix &lt;=V4V2Aainfix &lt;=V1V4Aainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="apermut_subV5V7V1ainfix +V2c1AaexchangeV5V7V3V4Iainfix =V7asetV6V4agetV5V3Aainfix &lt;=c0V0FAainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix =V6asetV5V3agetV5V4Aainfix &lt;=c0V0FAainfix &lt;V3V0Aainfix &lt;=c0V3Aainfix &lt;V4V0Aainfix &lt;=c0V4Aainfix &lt;V3V0Aainfix &lt;=c0V3Iainfix &lt;=V4V2Aainfix &lt;=V1V4Aainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
<label <label
name="expl:VC for exchange"/> name="expl:VC for exchange"/>
...@@ -48,7 +52,7 @@ ...@@ -48,7 +52,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="VC for partition_" expl="VC for partition_"
sum="bd2b572a9bc5cf0308acd8be49766159" sum="96b56b02850cec317d1336ee1cbfa06d"
proved="true" proved="true"
expanded="false" expanded="false"
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&lt;V59V54Aainfix &lt;=V1V59FAainfix =agetV55V4V5Aainfix &lt;agetV55V53V5Oainfix =V53V1Aainfix &gt;agetV55V54V5Oainfix =V54V2Aapermut_subV3V55V1ainfix +V2c1Aainfix &lt;=V54V2Aainfix &lt;=V53V54Aainfix &lt;=V1V53Aainfix &lt;=c0V0FAainfix =agetV50V4V5Aainfix &gt;=agetV50V60V5Iainfix &lt;=V60V2Aainfix &lt;V52V60FAainfix &lt;=agetV50V61V5Iainfix &lt;V61V51Aainfix &lt;=V1V61FAapermut_subV3V50V1ainfix +V2c1Aainfix &lt;=V51V2Aainfix &lt;=V1V51Aainfix &lt;=V52V2Aainfix &lt;=V1V52Aainfix &lt;ainfix -ainfix +c1V52V51ainfix -ainfix +c1V29V30Aainfix &lt;=c0ainfix -ainfix +c1V29V30Iainfix =V52ainfix -V33c1FIainfix =V51ainfix +V32c1FIapermut_subV31V50V1ainfix +V2c1AaexchangeV31V50V32V33Aainfix &lt;=c0V0FAainfix &lt;=V33V2Aainfix &lt;=V1V33Aainfix &lt;V2V0Aainfix &lt;=V32V2Aainfix &lt;=V1V32Aainfix &lt;=c0V1ainfix &lt;V32V33ainfix &lt;V62V33Aainfix &lt;=c0V33Aainfix &gt;=agetV31V63V5Iainfix &lt;=V63V2Aainfix &lt;V62V63FAainfix &lt;=V62V2Aainfix &lt;=V1V62Iainfix =V62ainfix -V33c1Fainfix &gt;=agetV31V33V5Aainfix &lt;V33V0Aainfix &lt;=c0V33ainfix &lt;V1V33Iainfix &gt;=agetV31V64V5Iainfix &lt;=V64V2Aainfix &lt;V33V64FAainfix &lt;=V33V2Aainfix &lt;=V1V33FAainfix &gt;=agetV31V65V5Iainfix &lt;=V65V2Aainfix &lt;V29V65FAainfix &lt;=V29V2Aainfix &lt;=V1V29iiiainfix &gt;=agetV31V67V5Iainfix &lt;=V67V2Aainfix &lt;V66V67FAainfix &lt;=agetV31V68V5Iainfix &lt;V68V32Aainfix &lt;=V1V68FAainfix =agetV31V4V5Aainfix &lt;agetV31V66V5Oainfix =V66V1Aainfix &gt;agetV31V32V5Oainfix =V32V2Aapermut_subV3V31V1ainfix +V2c1Aainfix &lt;=V32V2Aainfix &lt;=V66V32Aainfix &lt;=V1V66ainfix &gt;=agetV74V75V5Iainfix &lt;=V75V2Aainfix &lt;V72V75FAainfix &lt;=agetV74V76V5Iainfix &lt;V76V73Aainfix &lt;=V1V76FAainfix =agetV74V4V5Aainfix &lt;agetV74V72V5Oainfix =V72V1Aainfix &gt;agetV74V73V5Oainfix =V73V2Aapermut_subV3V74V1ainfix +V2c1Aainfix &lt;=V73V2Aainfix &lt;=V72V73Aainfix &lt;=V1V72Iainfix &gt;=agetV74V77V5Iainfix &lt;=V77V2Aainfix &lt;V72V77FAainfix &lt;=agetV74V78V5Iainfix &lt;V78V73Aainfix &lt;=V1V78FAainfix =agetV74V4V5Aainfix &lt;agetV74V72V5Oainfix =V72V1Aainfix &gt;agetV74V73V5Oainfix =V73V2Aapermut_subV3V74V1ainfix +V2c1Aainfix &lt;=V73V2Aainfix &lt;=V72V73Aainfix &lt;=V1V72Aainfix &lt;=c0V0FAainfix =agetV69V4V5Aainfix &gt;=agetV69V79V5Iainfix &lt;=V79V2Aainfix &lt;V71V79FAainfix &lt;=agetV69V80V5Iainfix &lt;V80V70Aainfix &lt;=V1V80FAapermut_subV3V69V1ainfix +V2c1Aainfix &lt;=V70V2Aainfix &lt;=V1V70Aainfix &lt;=V71V2Aainfix &lt;=V1V71Aainfix &lt;ainfix -ainfix +c1V71V70ainfix -ainfix +c1V29V30Aainfix &lt;=c0ainfix -ainfix +c1V29V30Iainfix =V71ainfix -V66c1FIainfix =V70ainfix +V32c1FIapermut_subV31V69V1ainfix +V2c1AaexchangeV31V69V32V66Aainfix &lt;=c0V0FAainfix &lt;=V66V2Aainfix &lt;=V1V66Aainfix &lt;V2V0Aainfix &lt;=V32V2Aainfix &lt;=V1V32Aainfix &lt;=c0V1ainfix &lt;V32V66iiainfix &gt;=agetV31V81V5Iainfix &lt;=V81V2Aainfix &lt;V66V81FAainfix &lt;=agetV31V82V5Iainfix &lt;V82V32Aainfix &lt;=V1V82FAainfix =agetV31V4V5Aainfix &lt;agetV31V66V5Oainfix =V66V1Aainfix &gt;agetV31V32V5Oainfix =V32V2Aapermut_subV3V31V1ainfix +V2c1Aainfix &lt;=V32V2Aainfix &lt;=V66V32Aainfix &lt;=V1V66ainfix &gt;=agetV88V89V5Iainfix &lt;=V89V2Aainfix &lt;V86V89FAainfix &lt;=agetV88V90V5Iainfix &lt;V90V87Aainfix &lt;=V1V90FAainfix =agetV88V4V5Aainfix &lt;agetV88V86V5Oainfix =V86V1Aainfix &gt;agetV88V87V5Oainfix =V87V2Aapermut_subV3V88V1ainfix +V2c1Aainfix &lt;=V87V2Aainfix &lt;=V86V87Aainfix &lt;=V1V86Iainfix &gt;=agetV88V91V5Iainfix &lt;=V91V2Aainfix &lt;V86V91FAainfix &lt;=agetV88V92V5Iainfix &lt;V92V87Aainfix &lt;=V1V92FAainfix =agetV88V4V5Aainfix &lt;agetV88V86V5Oainfix =V86V1Aainfix &gt;agetV88V87V5Oainfix =V87V2Aapermut_subV3V88V1ainfix +V2c1Aainfix &lt;=V87V2Aainfix &lt;=V86V87Aainfix &lt;=V1V86Aainfix &lt;=c0V0FAainfix =agetV83V4V5Aainfix &gt;=agetV83V93V5Iainfix &lt;=V93V2Aainfix &lt;V85V93FAainfix &lt;=agetV83V94V5Iainfix &lt;V94V84Aainfix &lt;=V1V94FAapermut_subV3V83V1ainfix +V2c1Aainfix &lt;=V84V2Aainfix &lt;=V1V84Aainfix &lt;=V85V2Aainfix &lt;=V1V85Aainfix &lt;ainfix -ainfix +c1V85V84ainfix -ainfix +c1V29V30Aainfix &lt;=c0ainfix -ainfix +c1V29V30Iainfix =V85ainfix -V66c1FIainfix =V84ainfix +V32c1FIapermut_subV31V83V1ainfix +V2c1AaexchangeV31V83V32V66Aainfix &lt;=c0V0FAainfix &lt;=V66V2Aainfix &lt;=V1V66Aainfix &lt;V2V0Aainfix &lt;=V32V2Aainfix &lt;=V1V32Aainfix &lt;=c0V1ainfix &lt;V32V66ainfix &lt;V95V66Aainfix &lt;=c0V66Aainfix &gt;=agetV31V96V5Iainfix &lt;=V96V2Aainfix &lt;V95V96FAainfix &lt;=V95V2Aainfix &lt;=V1V95Iainfix =V95ainfix -V66c1Fainfix &gt;=agetV31V66V5Aainfix &lt;V66V0Aainfix &lt;=c0V66ainfix &lt;V1V66Iainfix &gt;=agetV31V97V5Iainfix &lt;=V97V2Aainfix &lt;V66V97FAainfix &lt;=V66V2Aainfix &lt;=V1V66FAainfix &gt;=agetV31V98V5Iainfix &lt;=V98V2Aainfix &lt;V29V98FAainfix &lt;=V29V2Aainfix &lt;=V1V29ainfix &lt;ainfix -V2V99ainfix -V2V32Aainfix &lt;=c0ainfix -V2V32Aainfix &lt;=agetV31V100V5Iainfix &lt;V100V99Aainfix &lt;=V1V100FAainfix &lt;=V99V2Aainfix &lt;=V1V99Iainfix =V99ainfix +V32c1Fainfix &lt;=agetV31V32V5Aainfix &lt;V32V0Aainfix &lt;=c0V32ainfix &lt;V32V2Iainfix &lt;=agetV31V101V5Iainfix &lt;V101V32Aainfix &lt;=V1V101FAainfix &lt;=V32V2Aainfix &lt;=V1V32FAainfix &lt;=agetV31V102V5Iainfix &lt;V102V30Aainfix &lt;=V1V102FAainfix &lt;=V30V2Aainfix &lt;=V1V30Iainfix =agetV31V4V5Aainfix &gt;=agetV31V103V5Iainfix &lt;=V103V2Aainfix &lt;V29V103FAainfix &lt;=agetV31V104V5Iainfix &lt;V104V30Aainfix &lt;=V1V104FAapermut_subV3V31V1ainfix +V2c1Aainfix &lt;=V30V2Aainfix &lt;=V1V30Aainfix &lt;=V29V2Aainfix &lt;=V1V29Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Aainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -63,7 +67,7 @@ ...@@ -63,7 +67,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="1. precondition" expl="1. precondition"
sum="3797e16c7802bc7def87e4f3ce917860" sum="f5b03c1ac294fd80f568f5243b72bb40"
proved="true" proved="true"
expanded="false" expanded="false"
shape="preconditionainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="preconditionainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -83,7 +87,7 @@ ...@@ -83,7 +87,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="2. loop invariant init" expl="2. loop invariant init"
sum="42a07eaa024df266cae48615e49484d3" sum="a350a2bf5cf56e32deccf5b9c89b9233"
proved="true" proved="true"
expanded="false" expanded="false"
shape="loop invariant initainfix &lt;=V10V2Aainfix &lt;=V1V10Iainfix =agetV11V4V5Aainfix &gt;=agetV11V12V5Iainfix &lt;=V12V2Aainfix &lt;V9V12FAainfix &lt;=agetV11V13V5Iainfix &lt;V13V10Aainfix &lt;=V1V13FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="loop invariant initainfix &lt;=V10V2Aainfix &lt;=V1V10Iainfix =agetV11V4V5Aainfix &gt;=agetV11V12V5Iainfix &lt;=V12V2Aainfix &lt;V9V12FAainfix &lt;=agetV11V13V5Iainfix &lt;V13V10Aainfix &lt;=V1V13FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -103,7 +107,7 @@ ...@@ -103,7 +107,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="3. loop invariant init" expl="3. loop invariant init"
sum="f667c8592f472f3e4a31e3dd4ae0b638" sum="ae11939f427f925a69743f59300ad72a"
proved="true" proved="true"
expanded="false" expanded="false"
shape="loop invariant initainfix &lt;=agetV11V12V5Iainfix &lt;V12V10Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V13V5Iainfix &lt;=V13V2Aainfix &lt;V9V13FAainfix &lt;=agetV11V14V5Iainfix &lt;V14V10Aainfix &lt;=V1V14FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="loop invariant initainfix &lt;=agetV11V12V5Iainfix &lt;V12V10Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V13V5Iainfix &lt;=V13V2Aainfix &lt;V9V13FAainfix &lt;=agetV11V14V5Iainfix &lt;V14V10Aainfix &lt;=V1V14FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -123,7 +127,7 @@ ...@@ -123,7 +127,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="4. precondition" expl="4. precondition"
sum="7bfd3a4e6bff2c1420b71650615213e8" sum="6baaa60f588cbe07c458e6ff2ff0ae86"
proved="true" proved="true"
expanded="false" expanded="false"
shape="preconditionainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V13V5Iainfix &lt;V13V12Aainfix &lt;=V1V13FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V14V5Iainfix &lt;=V14V2Aainfix &lt;V9V14FAainfix &lt;=agetV11V15V5Iainfix &lt;V15V10Aainfix &lt;=V1V15FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="preconditionainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V13V5Iainfix &lt;V13V12Aainfix &lt;=V1V13FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V14V5Iainfix &lt;=V14V2Aainfix &lt;V9V14FAainfix &lt;=agetV11V15V5Iainfix &lt;V15V10Aainfix &lt;=V1V15FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -143,7 +147,7 @@ ...@@ -143,7 +147,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="5. loop invariant preservation" expl="5. loop invariant preservation"
sum="492bfde3d2973e8fcf28ec8a2fd6db08" sum="e54577966ef9b401bb80e81d5105fa3b"
proved="true" proved="true"
expanded="false" expanded="false"
shape="loop invariant preservationainfix &lt;=V13V2Aainfix &lt;=V1V13Iainfix =V13ainfix +V12c1FIainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V14V5Iainfix &lt;V14V12Aainfix &lt;=V1V14FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V15V5Iainfix &lt;=V15V2Aainfix &lt;V9V15FAainfix &lt;=agetV11V16V5Iainfix &lt;V16V10Aainfix &lt;=V1V16FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="loop invariant preservationainfix &lt;=V13V2Aainfix &lt;=V1V13Iainfix =V13ainfix +V12c1FIainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V14V5Iainfix &lt;V14V12Aainfix &lt;=V1V14FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V15V5Iainfix &lt;=V15V2Aainfix &lt;V9V15FAainfix &lt;=agetV11V16V5Iainfix &lt;V16V10Aainfix &lt;=V1V16FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -163,7 +167,7 @@ ...@@ -163,7 +167,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="6. loop invariant preservation" expl="6. loop invariant preservation"
sum="fff45d1a1f29fb2bbe023ee37455940b" sum="ab97e82694521a31cecec047597373cb"
proved="true" proved="true"
expanded="false" expanded="false"
shape="loop invariant preservationainfix &lt;=agetV11V14V5Iainfix &lt;V14V13Aainfix &lt;=V1V14FIainfix =V13ainfix +V12c1FIainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V15V5Iainfix &lt;V15V12Aainfix &lt;=V1V15FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V16V5Iainfix &lt;=V16V2Aainfix &lt;V9V16FAainfix &lt;=agetV11V17V5Iainfix &lt;V17V10Aainfix &lt;=V1V17FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="loop invariant preservationainfix &lt;=agetV11V14V5Iainfix &lt;V14V13Aainfix &lt;=V1V14FIainfix =V13ainfix +V12c1FIainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V15V5Iainfix &lt;V15V12Aainfix &lt;=V1V15FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V16V5Iainfix &lt;=V16V2Aainfix &lt;V9V16FAainfix &lt;=agetV11V17V5Iainfix &lt;V17V10Aainfix &lt;=V1V17FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -183,7 +187,7 @@ ...@@ -183,7 +187,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="7. loop variant decrease" expl="7. loop variant decrease"
sum="555ac37fafd3a769d1770c4142cbf038" sum="c63a729ff9066a11e3279138b85cbe96"
proved="true" proved="true"
expanded="false" expanded="false"
shape="loop variant decreaseainfix &lt;ainfix -V2V13ainfix -V2V12Aainfix &lt;=c0ainfix -V2V12Iainfix =V13ainfix +V12c1FIainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V14V5Iainfix &lt;V14V12Aainfix &lt;=V1V14FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V15V5Iainfix &lt;=V15V2Aainfix &lt;V9V15FAainfix &lt;=agetV11V16V5Iainfix &lt;V16V10Aainfix &lt;=V1V16FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="loop variant decreaseainfix &lt;ainfix -V2V13ainfix -V2V12Aainfix &lt;=c0ainfix -V2V12Iainfix =V13ainfix +V12c1FIainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V14V5Iainfix &lt;V14V12Aainfix &lt;=V1V14FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V15V5Iainfix &lt;=V15V2Aainfix &lt;V9V15FAainfix &lt;=agetV11V16V5Iainfix &lt;V16V10Aainfix &lt;=V1V16FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -203,7 +207,7 @@ ...@@ -203,7 +207,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="8. loop invariant init" expl="8. loop invariant init"
sum="6a205fc128b593723610123e77714f03" sum="8b957f45e8ca7e6c62c4dbc48e4e0a6a"
proved="true" proved="true"
expanded="false" expanded="false"
shape="loop invariant initainfix &lt;=V9V2Aainfix &lt;=V1V9INainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V13V5Iainfix &lt;V13V12Aainfix &lt;=V1V13FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V14V5Iainfix &lt;=V14V2Aainfix &lt;V9V14FAainfix &lt;=agetV11V15V5Iainfix &lt;V15V10Aainfix &lt;=V1V15FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="loop invariant initainfix &lt;=V9V2Aainfix &lt;=V1V9INainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V13V5Iainfix &lt;V13V12Aainfix &lt;=V1V13FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V14V5Iainfix &lt;=V14V2Aainfix &lt;V9V14FAainfix &lt;=agetV11V15V5Iainfix &lt;V15V10Aainfix &lt;=V1V15FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -223,7 +227,7 @@ ...@@ -223,7 +227,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="9. loop invariant init" expl="9. loop invariant init"
sum="aa67b40fb87098572f2ae5fad1602831" sum="f17cba729df6c11d3f0935519c59ddc3"
proved="true" proved="true"
expanded="false" expanded="false"
shape="loop invariant initainfix &gt;=agetV11V13V5Iainfix &lt;=V13V2Aainfix &lt;V9V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V14V5Iainfix &lt;V14V12Aainfix &lt;=V1V14FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V15V5Iainfix &lt;=V15V2Aainfix &lt;V9V15FAainfix &lt;=agetV11V16V5Iainfix &lt;V16V10Aainfix &lt;=V1V16FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="loop invariant initainfix &gt;=agetV11V13V5Iainfix &lt;=V13V2Aainfix &lt;V9V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V14V5Iainfix &lt;V14V12Aainfix &lt;=V1V14FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V15V5Iainfix &lt;=V15V2Aainfix &lt;V9V15FAainfix &lt;=agetV11V16V5Iainfix &lt;V16V10Aainfix &lt;=V1V16FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -243,7 +247,7 @@ ...@@ -243,7 +247,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="10. precondition" expl="10. precondition"
sum="754d1b3f070b9ac3104c3f0697fa25fc" sum="ffba21c2b05913cd8445ac42a3afe150"
proved="true" proved="true"
expanded="false" expanded="false"
shape="preconditionainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V14V5Iainfix &lt;=V14V2Aainfix &lt;V13V14FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V15V5Iainfix &lt;V15V12Aainfix &lt;=V1V15FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V16V5Iainfix &lt;=V16V2Aainfix &lt;V9V16FAainfix &lt;=agetV11V17V5Iainfix &lt;V17V10Aainfix &lt;=V1V17FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="preconditionainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V14V5Iainfix &lt;=V14V2Aainfix &lt;V13V14FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V15V5Iainfix &lt;V15V12Aainfix &lt;=V1V15FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V16V5Iainfix &lt;=V16V2Aainfix &lt;V9V16FAainfix &lt;=agetV11V17V5Iainfix &lt;V17V10Aainfix &lt;=V1V17FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -263,7 +267,7 @@ ...@@ -263,7 +267,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="11. loop invariant preservation" expl="11. loop invariant preservation"
sum="1758ebd0522bca6ef1313a5130e7d03a" sum="39087b56eb74e0526bb6daf2a6e26a34"
proved="true" proved="true"
expanded="false" expanded="false"
shape="loop invariant preservationainfix &lt;=V14V2Aainfix &lt;=V1V14Iainfix =V14ainfix -V13c1FIainfix &gt;=agetV11V13V5Iainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V15V5Iainfix &lt;=V15V2Aainfix &lt;V13V15FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V16V5Iainfix &lt;V16V12Aainfix &lt;=V1V16FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V17V5Iainfix &lt;=V17V2Aainfix &lt;V9V17FAainfix &lt;=agetV11V18V5Iainfix &lt;V18V10Aainfix &lt;=V1V18FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="loop invariant preservationainfix &lt;=V14V2Aainfix &lt;=V1V14Iainfix =V14ainfix -V13c1FIainfix &gt;=agetV11V13V5Iainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V15V5Iainfix &lt;=V15V2Aainfix &lt;V13V15FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V16V5Iainfix &lt;V16V12Aainfix &lt;=V1V16FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V17V5Iainfix &lt;=V17V2Aainfix &lt;V9V17FAainfix &lt;=agetV11V18V5Iainfix &lt;V18V10Aainfix &lt;=V1V18FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -283,7 +287,7 @@ ...@@ -283,7 +287,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="12. loop invariant preservation" expl="12. loop invariant preservation"
sum="b3d9990aca52a8c787421695dbdd0ad8" sum="13c90cdd60d5392b9c7b47f1ac1cea7d"
proved="true" proved="true"
expanded="false" expanded="false"
shape="loop invariant preservationainfix &gt;=agetV11V15V5Iainfix &lt;=V15V2Aainfix &lt;V14V15FIainfix =V14ainfix -V13c1FIainfix &gt;=agetV11V13V5Iainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V16V5Iainfix &lt;=V16V2Aainfix &lt;V13V16FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V17V5Iainfix &lt;V17V12Aainfix &lt;=V1V17FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V18V5Iainfix &lt;=V18V2Aainfix &lt;V9V18FAainfix &lt;=agetV11V19V5Iainfix &lt;V19V10Aainfix &lt;=V1V19FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="loop invariant preservationainfix &gt;=agetV11V15V5Iainfix &lt;=V15V2Aainfix &lt;V14V15FIainfix =V14ainfix -V13c1FIainfix &gt;=agetV11V13V5Iainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V16V5Iainfix &lt;=V16V2Aainfix &lt;V13V16FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V17V5Iainfix &lt;V17V12Aainfix &lt;=V1V17FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V18V5Iainfix &lt;=V18V2Aainfix &lt;V9V18FAainfix &lt;=agetV11V19V5Iainfix &lt;V19V10Aainfix &lt;=V1V19FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -303,7 +307,7 @@ ...@@ -303,7 +307,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="13. loop variant decrease" expl="13. loop variant decrease"
sum="06ea7bc58c3020ffd485c2d40add590a" sum="0f5f7e7628ac38902a0a61cdb9d55159"
proved="true" proved="true"
expanded="false" expanded="false"
shape="loop variant decreaseainfix &lt;V14V13Aainfix &lt;=c0V13Iainfix =V14ainfix -V13c1FIainfix &gt;=agetV11V13V5Iainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V15V5Iainfix &lt;=V15V2Aainfix &lt;V13V15FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V16V5Iainfix &lt;V16V12Aainfix &lt;=V1V16FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V17V5Iainfix &lt;=V17V2Aainfix &lt;V9V17FAainfix &lt;=agetV11V18V5Iainfix &lt;V18V10Aainfix &lt;=V1V18FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="loop variant decreaseainfix &lt;V14V13Aainfix &lt;=c0V13Iainfix =V14ainfix -V13c1FIainfix &gt;=agetV11V13V5Iainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V15V5Iainfix &lt;=V15V2Aainfix &lt;V13V15FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V16V5Iainfix &lt;V16V12Aainfix &lt;=V1V16FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V17V5Iainfix &lt;=V17V2Aainfix &lt;V9V17FAainfix &lt;=agetV11V18V5Iainfix &lt;V18V10Aainfix &lt;=V1V18FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -323,7 +327,7 @@ ...@@ -323,7 +327,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="14. precondition" expl="14. precondition"
sum="99cc4f993b42485fb9cfef763ca8dfb8" sum="4e6168c31d40851b6eda1dba4e587f3f"
proved="true" proved="true"
expanded="false" expanded="false"
shape="preconditionainfix &lt;=V13V2Aainfix &lt;=V1V13Aainfix &lt;V2V0Aainfix &lt;=V12V2Aainfix &lt;=V1V12Aainfix &lt;=c0V1Iainfix &lt;V12V13INainfix &gt;=agetV11V13V5Iainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V14V5Iainfix &lt;=V14V2Aainfix &lt;V13V14FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V15V5Iainfix &lt;V15V12Aainfix &lt;=V1V15FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V16V5Iainfix &lt;=V16V2Aainfix &lt;V9V16FAainfix &lt;=agetV11V17V5Iainfix &lt;V17V10Aainfix &lt;=V1V17FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="preconditionainfix &lt;=V13V2Aainfix &lt;=V1V13Aainfix &lt;V2V0Aainfix &lt;=V12V2Aainfix &lt;=V1V12Aainfix &lt;=c0V1Iainfix &lt;V12V13INainfix &gt;=agetV11V13V5Iainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V14V5Iainfix &lt;=V14V2Aainfix &lt;V13V14FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V15V5Iainfix &lt;V15V12Aainfix &lt;=V1V15FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V16V5Iainfix &lt;=V16V2Aainfix &lt;V9V16FAainfix &lt;=agetV11V17V5Iainfix &lt;V17V10Aainfix &lt;=V1V17FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -351,7 +355,7 @@ ...@@ -351,7 +355,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="15. variant decrease" expl="15. variant decrease"
sum="2e87a1500cca72bf050e0d3ce76d84fb" sum="74073f0f7a661b71c2c3bd911a3d1a4e"
proved="true" proved="true"
expanded="false" expanded="false"
shape="variant decreaseainfix &lt;ainfix -ainfix +c1V16V15ainfix -ainfix +c1V9V10Aainfix &lt;=c0ainfix -ainfix +c1V9V10Iainfix =V16ainfix -V13c1FIainfix =V15ainfix +V12c1FIapermut_subV11V14V1ainfix +V2c1AaexchangeV11V14V12V13Aainfix &lt;=c0V0FIainfix &lt;=V13V2Aainfix &lt;=V1V13Aainfix &lt;V2V0Aainfix &lt;=V12V2Aainfix &lt;=V1V12Aainfix &lt;=c0V1Iainfix &lt;V12V13INainfix &gt;=agetV11V13V5Iainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V17V5Iainfix &lt;=V17V2Aainfix &lt;V13V17FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V18V5Iainfix &lt;V18V12Aainfix &lt;=V1V18FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V19V5Iainfix &lt;=V19V2Aainfix &lt;V9V19FAainfix &lt;=agetV11V20V5Iainfix &lt;V20V10Aainfix &lt;=V1V20FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="variant decreaseainfix &lt;ainfix -ainfix +c1V16V15ainfix -ainfix +c1V9V10Aainfix &lt;=c0ainfix -ainfix +c1V9V10Iainfix =V16ainfix -V13c1FIainfix =V15ainfix +V12c1FIapermut_subV11V14V1ainfix +V2c1AaexchangeV11V14V12V13Aainfix &lt;=c0V0FIainfix &lt;=V13V2Aainfix &lt;=V1V13Aainfix &lt;V2V0Aainfix &lt;=V12V2Aainfix &lt;=V1V12Aainfix &lt;=c0V1Iainfix &lt;V12V13INainfix &gt;=agetV11V13V5Iainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V17V5Iainfix &lt;=V17V2Aainfix &lt;V13V17FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V18V5Iainfix &lt;V18V12Aainfix &lt;=V1V18FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V19V5Iainfix &lt;=V19V2Aainfix &lt;V9V19FAainfix &lt;=agetV11V20V5Iainfix &lt;V20V10Aainfix &lt;=V1V20FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -371,7 +375,7 @@ ...@@ -371,7 +375,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="16. precondition" expl="16. precondition"
sum="891fdf468e7b86ab32a0f197567ba896" sum="6ffec341bf22e4d7e59beea7769b10f2"
proved="true" proved="true"
expanded="false" expanded="false"
shape="preconditionainfix &lt;=V15V2Aainfix &lt;=V1V15Aainfix &lt;=V16V2Aainfix &lt;=V1V16Iainfix =V16ainfix -V13c1FIainfix =V15ainfix +V12c1FIapermut_subV11V14V1ainfix +V2c1AaexchangeV11V14V12V13Aainfix &lt;=c0V0FIainfix &lt;=V13V2Aainfix &lt;=V1V13Aainfix &lt;V2V0Aainfix &lt;=V12V2Aainfix &lt;=V1V12Aainfix &lt;=c0V1Iainfix &lt;V12V13INainfix &gt;=agetV11V13V5Iainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V17V5Iainfix &lt;=V17V2Aainfix &lt;V13V17FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V18V5Iainfix &lt;V18V12Aainfix &lt;=V1V18FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V19V5Iainfix &lt;=V19V2Aainfix &lt;V9V19FAainfix &lt;=agetV11V20V5Iainfix &lt;V20V10Aainfix &lt;=V1V20FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="preconditionainfix &lt;=V15V2Aainfix &lt;=V1V15Aainfix &lt;=V16V2Aainfix &lt;=V1V16Iainfix =V16ainfix -V13c1FIainfix =V15ainfix +V12c1FIapermut_subV11V14V1ainfix +V2c1AaexchangeV11V14V12V13Aainfix &lt;=c0V0FIainfix &lt;=V13V2Aainfix &lt;=V1V13Aainfix &lt;V2V0Aainfix &lt;=V12V2Aainfix &lt;=V1V12Aainfix &lt;=c0V1Iainfix &lt;V12V13INainfix &gt;=agetV11V13V5Iainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V17V5Iainfix &lt;=V17V2Aainfix &lt;V13V17FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V18V5Iainfix &lt;V18V12Aainfix &lt;=V1V18FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V19V5Iainfix &lt;=V19V2Aainfix &lt;V9V19FAainfix &lt;=agetV11V20V5Iainfix &lt;V20V10Aainfix &lt;=V1V20FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -391,7 +395,7 @@ ...@@ -391,7 +395,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="17. precondition" expl="17. precondition"
sum="859d0c44df9a944e23954e48a5be4e52" sum="808812baf2fd6747b3c8aab52fb16fa8"
proved="true" proved="true"
expanded="false" expanded="false"
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...@@ -411,7 +415,7 @@ ...@@ -411,7 +415,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
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expl="18. precondition" expl="18. precondition"
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expanded="false" expanded="false"
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...@@ -431,7 +435,7 @@ ...@@ -431,7 +435,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="19. precondition" expl="19. precondition"
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expanded="false" expanded="false"
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...@@ -451,7 +455,7 @@ ...@@ -451,7 +455,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="20. precondition" expl="20. precondition"
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proved="true" proved="true"
expanded="false" expanded="false"
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...@@ -471,7 +475,7 @@ ...@@ -471,7 +475,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="21. postcondition" expl="21. postcondition"
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...@@ -491,7 +495,7 @@ ...@@ -491,7 +495,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
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proved="true" proved="true"
expanded="false" expanded="false"
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...@@ -511,7 +515,7 @@ ...@@ -511,7 +515,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="23. postcondition" expl="23. postcondition"
sum="9eead6e46ea451e25168d50e81a7dfbb" sum="b30efbddf4c30acf1b43496dbedeef05"
proved="true" proved="true"
expanded="false" expanded="false"
shape="postconditionainfix &gt;agetV19V18V5Oainfix =V18V2Iainfix &gt;=agetV19V20V5Iainfix &lt;=V20V2Aainfix &lt;V17V20FAainfix &lt;=agetV19V21V5Iainfix &lt;V21V18Aainfix &lt;=V1V21FAainfix =agetV19V4V5Aainfix &lt;agetV19V17V5Oainfix =V17V1Aainfix &gt;agetV19V18V5Oainfix =V18V2Aapermut_subV3V19V1ainfix +V2c1Aainfix &lt;=V18V2Aainfix &lt;=V17V18Aainfix &lt;=V1V17Aainfix &lt;=c0V0FIainfix =agetV14V4V5Aainfix &gt;=agetV14V22V5Iainfix &lt;=V22V2Aainfix &lt;V16V22FAainfix &lt;=agetV14V23V5Iainfix &lt;V23V15Aainfix &lt;=V1V23FAapermut_subV3V14V1ainfix +V2c1Aainfix &lt;=V15V2Aainfix &lt;=V1V15Aainfix &lt;=V16V2Aainfix &lt;=V1V16Iainfix =V16ainfix -V13c1FIainfix =V15ainfix +V12c1FIapermut_subV11V14V1ainfix +V2c1AaexchangeV11V14V12V13Aainfix &lt;=c0V0FIainfix &lt;=V13V2Aainfix &lt;=V1V13Aainfix &lt;V2V0Aainfix &lt;=V12V2Aainfix &lt;=V1V12Aainfix &lt;=c0V1Iainfix &lt;V12V13INainfix &gt;=agetV11V13V5Iainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V24V5Iainfix &lt;=V24V2Aainfix &lt;V13V24FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V25V5Iainfix &lt;V25V12Aainfix &lt;=V1V25FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V26V5Iainfix &lt;=V26V2Aainfix &lt;V9V26FAainfix &lt;=agetV11V27V5Iainfix &lt;V27V10Aainfix &lt;=V1V27FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="postconditionainfix &gt;agetV19V18V5Oainfix =V18V2Iainfix &gt;=agetV19V20V5Iainfix &lt;=V20V2Aainfix &lt;V17V20FAainfix &lt;=agetV19V21V5Iainfix &lt;V21V18Aainfix &lt;=V1V21FAainfix =agetV19V4V5Aainfix &lt;agetV19V17V5Oainfix =V17V1Aainfix &gt;agetV19V18V5Oainfix =V18V2Aapermut_subV3V19V1ainfix +V2c1Aainfix &lt;=V18V2Aainfix &lt;=V17V18Aainfix &lt;=V1V17Aainfix &lt;=c0V0FIainfix =agetV14V4V5Aainfix &gt;=agetV14V22V5Iainfix &lt;=V22V2Aainfix &lt;V16V22FAainfix &lt;=agetV14V23V5Iainfix &lt;V23V15Aainfix &lt;=V1V23FAapermut_subV3V14V1ainfix +V2c1Aainfix &lt;=V15V2Aainfix &lt;=V1V15Aainfix &lt;=V16V2Aainfix &lt;=V1V16Iainfix =V16ainfix -V13c1FIainfix =V15ainfix +V12c1FIapermut_subV11V14V1ainfix +V2c1AaexchangeV11V14V12V13Aainfix &lt;=c0V0FIainfix &lt;=V13V2Aainfix &lt;=V1V13Aainfix &lt;V2V0Aainfix &lt;=V12V2Aainfix &lt;=V1V12Aainfix &lt;=c0V1Iainfix &lt;V12V13INainfix &gt;=agetV11V13V5Iainfix &lt;V13V0Aainfix &lt;=c0V13Iainfix &lt;V1V13Iainfix &gt;=agetV11V24V5Iainfix &lt;=V24V2Aainfix &lt;V13V24FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V25V5Iainfix &lt;V25V12Aainfix &lt;=V1V25FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V26V5Iainfix &lt;=V26V2Aainfix &lt;V9V26FAainfix &lt;=agetV11V27V5Iainfix &lt;V27V10Aainfix &lt;=V1V27FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -531,7 +535,7 @@ ...@@ -531,7 +535,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="24. postcondition" expl="24. postcondition"
sum="7d70b889effc21221ad5ec86ecb7157d" sum="b08448b45541aff2e9dc12956509affb"
proved="true" proved="true"
expanded="false" expanded="false"
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...@@ -551,7 +555,7 @@ ...@@ -551,7 +555,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="25. postcondition" expl="25. postcondition"
sum="a4d82b487d68deb3d591155ac15bda2b" sum="45b9e0dc142ddf0e87def05f6a167fd3"
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expanded="false" expanded="false"
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...@@ -571,7 +575,7 @@ ...@@ -571,7 +575,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
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...@@ -591,7 +595,7 @@ ...@@ -591,7 +595,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
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...@@ -611,7 +615,7 @@ ...@@ -611,7 +615,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
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...@@ -631,7 +635,7 @@ ...@@ -631,7 +635,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
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...@@ -651,7 +655,7 @@ ...@@ -651,7 +655,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="30. postcondition" expl="30. postcondition"
sum="a4174f3fd469ee9cb9b614ed5e54bdab" sum="d8c74de0215cf79d8aaf7c7c9e0a06e4"
proved="true" proved="true"
expanded="false" expanded="false"
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...@@ -671,7 +675,7 @@ ...@@ -671,7 +675,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="31. postcondition" expl="31. postcondition"
sum="758394a42f796579c42d2d24176fb475" sum="3c33e97d4b2b54113f9101683df2f35b"
proved="true" proved="true"
expanded="false" expanded="false"
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...@@ -691,7 +695,7 @@ ...@@ -691,7 +695,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="32. postcondition" expl="32. postcondition"
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proved="true" proved="true"
expanded="false" expanded="false"
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...@@ -711,7 +715,7 @@ ...@@ -711,7 +715,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="33. postcondition" expl="33. postcondition"
sum="5523764276759c781e0fb8bd8f4a1c83" sum="99c29f6bfd02f130fcaa8ba3b90524e9"
proved="true" proved="true"
expanded="false" expanded="false"
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...@@ -731,7 +735,7 @@ ...@@ -731,7 +735,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="34. postcondition" expl="34. postcondition"
sum="844a10f30d7d3e94bbc7f2d7bfcbd5b7" sum="af11365188b8dd8bb7e868213e9300da"
proved="true" proved="true"
expanded="false" expanded="false"
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...@@ -751,7 +755,7 @@ ...@@ -751,7 +755,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="35. precondition" expl="35. precondition"
sum="e3cc6b6fcf403e801fa08a483d740021" sum="8f636096a3aa7b964ac098fd4341aeff"
proved="true" proved="true"
expanded="false" expanded="false"
shape="preconditionainfix &lt;=V13V2Aainfix &lt;=V1V13Aainfix &lt;V2V0Aainfix &lt;=V12V2Aainfix &lt;=V1V12Aainfix &lt;=c0V1Iainfix &lt;V12V13INainfix &lt;V1V13Iainfix &gt;=agetV11V14V5Iainfix &lt;=V14V2Aainfix &lt;V13V14FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V15V5Iainfix &lt;V15V12Aainfix &lt;=V1V15FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V16V5Iainfix &lt;=V16V2Aainfix &lt;V9V16FAainfix &lt;=agetV11V17V5Iainfix &lt;V17V10Aainfix &lt;=V1V17FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="preconditionainfix &lt;=V13V2Aainfix &lt;=V1V13Aainfix &lt;V2V0Aainfix &lt;=V12V2Aainfix &lt;=V1V12Aainfix &lt;=c0V1Iainfix &lt;V12V13INainfix &lt;V1V13Iainfix &gt;=agetV11V14V5Iainfix &lt;=V14V2Aainfix &lt;V13V14FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V15V5Iainfix &lt;V15V12Aainfix &lt;=V1V15FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V16V5Iainfix &lt;=V16V2Aainfix &lt;V9V16FAainfix &lt;=agetV11V17V5Iainfix &lt;V17V10Aainfix &lt;=V1V17FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -771,7 +775,7 @@ ...@@ -771,7 +775,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="36. variant decrease" expl="36. variant decrease"
sum="f48ddb9322d7c431663da1be29bd4c5a" sum="a8566513ea1d2dbd383e3557dbe4150c"
proved="true" proved="true"
expanded="false" expanded="false"
shape="variant decreaseainfix &lt;ainfix -ainfix +c1V16V15ainfix -ainfix +c1V9V10Aainfix &lt;=c0ainfix -ainfix +c1V9V10Iainfix =V16ainfix -V13c1FIainfix =V15ainfix +V12c1FIapermut_subV11V14V1ainfix +V2c1AaexchangeV11V14V12V13Aainfix &lt;=c0V0FIainfix &lt;=V13V2Aainfix &lt;=V1V13Aainfix &lt;V2V0Aainfix &lt;=V12V2Aainfix &lt;=V1V12Aainfix &lt;=c0V1Iainfix &lt;V12V13INainfix &lt;V1V13Iainfix &gt;=agetV11V17V5Iainfix &lt;=V17V2Aainfix &lt;V13V17FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V18V5Iainfix &lt;V18V12Aainfix &lt;=V1V18FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V19V5Iainfix &lt;=V19V2Aainfix &lt;V9V19FAainfix &lt;=agetV11V20V5Iainfix &lt;V20V10Aainfix &lt;=V1V20FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="variant decreaseainfix &lt;ainfix -ainfix +c1V16V15ainfix -ainfix +c1V9V10Aainfix &lt;=c0ainfix -ainfix +c1V9V10Iainfix =V16ainfix -V13c1FIainfix =V15ainfix +V12c1FIapermut_subV11V14V1ainfix +V2c1AaexchangeV11V14V12V13Aainfix &lt;=c0V0FIainfix &lt;=V13V2Aainfix &lt;=V1V13Aainfix &lt;V2V0Aainfix &lt;=V12V2Aainfix &lt;=V1V12Aainfix &lt;=c0V1Iainfix &lt;V12V13INainfix &lt;V1V13Iainfix &gt;=agetV11V17V5Iainfix &lt;=V17V2Aainfix &lt;V13V17FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V18V5Iainfix &lt;V18V12Aainfix &lt;=V1V18FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V19V5Iainfix &lt;=V19V2Aainfix &lt;V9V19FAainfix &lt;=agetV11V20V5Iainfix &lt;V20V10Aainfix &lt;=V1V20FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -791,7 +795,7 @@ ...@@ -791,7 +795,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="37. precondition" expl="37. precondition"
sum="91ff331ee8ee3777f21ab64400b06aae" sum="e4202045b0a4893c5d5f394d7c42b1fb"
proved="true" proved="true"
expanded="false" expanded="false"
shape="preconditionainfix &lt;=V15V2Aainfix &lt;=V1V15Aainfix &lt;=V16V2Aainfix &lt;=V1V16Iainfix =V16ainfix -V13c1FIainfix =V15ainfix +V12c1FIapermut_subV11V14V1ainfix +V2c1AaexchangeV11V14V12V13Aainfix &lt;=c0V0FIainfix &lt;=V13V2Aainfix &lt;=V1V13Aainfix &lt;V2V0Aainfix &lt;=V12V2Aainfix &lt;=V1V12Aainfix &lt;=c0V1Iainfix &lt;V12V13INainfix &lt;V1V13Iainfix &gt;=agetV11V17V5Iainfix &lt;=V17V2Aainfix &lt;V13V17FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V18V5Iainfix &lt;V18V12Aainfix &lt;=V1V18FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V19V5Iainfix &lt;=V19V2Aainfix &lt;V9V19FAainfix &lt;=agetV11V20V5Iainfix &lt;V20V10Aainfix &lt;=V1V20FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF"> shape="preconditionainfix &lt;=V15V2Aainfix &lt;=V1V15Aainfix &lt;=V16V2Aainfix &lt;=V1V16Iainfix =V16ainfix -V13c1FIainfix =V15ainfix +V12c1FIapermut_subV11V14V1ainfix +V2c1AaexchangeV11V14V12V13Aainfix &lt;=c0V0FIainfix &lt;=V13V2Aainfix &lt;=V1V13Aainfix &lt;V2V0Aainfix &lt;=V12V2Aainfix &lt;=V1V12Aainfix &lt;=c0V1Iainfix &lt;V12V13INainfix &lt;V1V13Iainfix &gt;=agetV11V17V5Iainfix &lt;=V17V2Aainfix &lt;V13V17FAainfix &lt;=V13V2Aainfix &lt;=V1V13FINainfix &lt;=agetV11V12V5Iainfix &lt;V12V0Aainfix &lt;=c0V12Iainfix &lt;V12V2Iainfix &lt;=agetV11V18V5Iainfix &lt;V18V12Aainfix &lt;=V1V18FAainfix &lt;=V12V2Aainfix &lt;=V1V12FIainfix =agetV11V4V5Aainfix &gt;=agetV11V19V5Iainfix &lt;=V19V2Aainfix &lt;V9V19FAainfix &lt;=agetV11V20V5Iainfix &lt;V20V10Aainfix &lt;=V1V20FAapermut_subV3V11V1ainfix +V2c1Aainfix &lt;=V10V2Aainfix &lt;=V1V10Aainfix &lt;=V9V2Aainfix &lt;=V1V9Aainfix &lt;=c0V0FIainfix =V8V2FIainfix =V7V1FIainfix =V6V5FLagetV3V4Iainfix &lt;V4V0Aainfix &lt;=c0V4Iainfix &lt;=V4V2Aainfix &lt;=V1V4FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
...@@ -811,7 +815,7 @@ ...@@ -811,7 +815,7 @@
locfile="../algo63.mlw" locfile="../algo63.mlw"
loclnum="33" loccnumb="6" loccnume="16" loclnum="33" loccnumb="6" loccnume="16"
expl="38. precondition" expl="38. precondition"
sum="1c7f978dbac25c45a12eefbc1b6ff8c7" sum="a534e27f8d9407491b97aef080ac180c"
proved="true" proved="true"
expanded="false" expanded="false"