Commit 9bf1998f authored by Andrei Paskevich's avatar Andrei Paskevich

update sessions (in progress)

parent ac976a84
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......@@ -28,7 +28,7 @@
locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19"
expl="VC for quicksort"
sum="ab2a63ccffd01ef10ebb7dc0e7571df9"
sum="58fde39b3de57a13ada8d66fc6adb75e"
proved="true"
expanded="true"
shape="iasorted_subV3V1ainfix +V2c1Aapermut_subV3V3V1ainfix +V2c1asorted_subV8V1ainfix +V2c1Aapermut_subV3V8V1ainfix +V2c1Aapermut_subV7V8V1ainfix +V2c1Iasorted_subV8V5ainfix +V2c1Aapermut_subV7V8V5ainfix +V2c1Aainfix <=c0V0FAainfix <V2V0Aainfix <=V5V2Aainfix <=c0V5Aainfix <ainfix -V2V5ainfix -V2V1Aainfix <=c0ainfix -V2V1Aapermut_subV6V7V1ainfix +V2c1Iasorted_subV7V1ainfix +V4c1Aapermut_subV6V7V1ainfix +V4c1Aainfix <=c0V0FAainfix <V4V0Aainfix <=V1V4Aainfix <=c0V1Aainfix <ainfix -V4V1ainfix -V2V1Aainfix <=c0ainfix -V2V1Iainfix >=agetV6V10V9Iainfix <=V10V2Aainfix <=V5V10FAainfix =agetV6V11V9Iainfix <V11V5Aainfix <V4V11FAainfix <=agetV6V12V9Iainfix <=V12V4Aainfix <=V1V12FEAapermut_subV3V6V1ainfix +V2c1Aainfix <=V5V2Aainfix <V4V5Aainfix <=V1V4Aainfix <=c0V0FAainfix <V2V0Aainfix <V1V2Aainfix <=c0V1ainfix <V1V2Iainfix <V2V0Aainfix <=V1V2Aainfix <=c0V1Aainfix <=c0V0FF">
......@@ -43,7 +43,7 @@
locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19"
expl="1. precondition"
sum="153b0a4ec87c1b7e4f4d4bc2ccec7568"
sum="3c43f6f2c8269df69c948249e7e1e382"
proved="true"
expanded="true"
shape="preconditionainfix <V2V0Aainfix <V1V2Aainfix <=c0V1Iainfix <V1V2Iainfix <V2V0Aainfix <=V1V2Aainfix <=c0V1Aainfix <=c0V0FF">
......@@ -63,7 +63,7 @@
locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19"
expl="2. variant decrease"
sum="d52fa8437c333e33dfcab95b688273a1"
sum="e4af12d56325fd83d45591296cbe3447"
proved="true"
expanded="true"
shape="variant decreaseainfix <ainfix -V4V1ainfix -V2V1Aainfix <=c0ainfix -V2V1Iainfix >=agetV6V8V7Iainfix <=V8V2Aainfix <=V5V8FAainfix =agetV6V9V7Iainfix <V9V5Aainfix <V4V9FAainfix <=agetV6V10V7Iainfix <=V10V4Aainfix <=V1V10FEAapermut_subV3V6V1ainfix +V2c1Aainfix <=V5V2Aainfix <V4V5Aainfix <=V1V4Aainfix <=c0V0FIainfix <V2V0Aainfix <V1V2Aainfix <=c0V1Iainfix <V1V2Iainfix <V2V0Aainfix <=V1V2Aainfix <=c0V1Aainfix <=c0V0FF">
......@@ -83,7 +83,7 @@
locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19"
expl="3. precondition"
sum="d824dc170165d3d1bd7f3e8aa5e84688"
sum="6b486a7a19953085f8a449593e49e9e3"
proved="true"
expanded="true"
shape="preconditionainfix <V4V0Aainfix <=V1V4Aainfix <=c0V1Iainfix >=agetV6V8V7Iainfix <=V8V2Aainfix <=V5V8FAainfix =agetV6V9V7Iainfix <V9V5Aainfix <V4V9FAainfix <=agetV6V10V7Iainfix <=V10V4Aainfix <=V1V10FEAapermut_subV3V6V1ainfix +V2c1Aainfix <=V5V2Aainfix <V4V5Aainfix <=V1V4Aainfix <=c0V0FIainfix <V2V0Aainfix <V1V2Aainfix <=c0V1Iainfix <V1V2Iainfix <V2V0Aainfix <=V1V2Aainfix <=c0V1Aainfix <=c0V0FF">
......@@ -103,7 +103,7 @@
locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19"
expl="4. assertion"
sum="a2985e78ef08b400f95948a9160374ea"
sum="b203e24ff20076cb2659b3454a5a6012"
proved="true"
expanded="true"
shape="assertionapermut_subV6V7V1ainfix +V2c1Iasorted_subV7V1ainfix +V4c1Aapermut_subV6V7V1ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V1V4Aainfix <=c0V1Iainfix >=agetV6V9V8Iainfix <=V9V2Aainfix <=V5V9FAainfix =agetV6V10V8Iainfix <V10V5Aainfix <V4V10FAainfix <=agetV6V11V8Iainfix <=V11V4Aainfix <=V1V11FEAapermut_subV3V6V1ainfix +V2c1Aainfix <=V5V2Aainfix <V4V5Aainfix <=V1V4Aainfix <=c0V0FIainfix <V2V0Aainfix <V1V2Aainfix <=c0V1Iainfix <V1V2Iainfix <V2V0Aainfix <=V1V2Aainfix <=c0V1Aainfix <=c0V0FF">
......@@ -123,7 +123,7 @@
locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19"
expl="5. variant decrease"
sum="f1c89158dd889a67f6ec2b53de972207"
sum="6cf15418ef8d15af54e3962c629dabd3"
proved="true"
expanded="true"
shape="variant decreaseainfix <ainfix -V2V5ainfix -V2V1Aainfix <=c0ainfix -V2V1Iapermut_subV6V7V1ainfix +V2c1Iasorted_subV7V1ainfix +V4c1Aapermut_subV6V7V1ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V1V4Aainfix <=c0V1Iainfix >=agetV6V9V8Iainfix <=V9V2Aainfix <=V5V9FAainfix =agetV6V10V8Iainfix <V10V5Aainfix <V4V10FAainfix <=agetV6V11V8Iainfix <=V11V4Aainfix <=V1V11FEAapermut_subV3V6V1ainfix +V2c1Aainfix <=V5V2Aainfix <V4V5Aainfix <=V1V4Aainfix <=c0V0FIainfix <V2V0Aainfix <V1V2Aainfix <=c0V1Iainfix <V1V2Iainfix <V2V0Aainfix <=V1V2Aainfix <=c0V1Aainfix <=c0V0FF">
......@@ -143,7 +143,7 @@
locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19"
expl="6. precondition"
sum="74c8e5dfdcaff3e9e3b7cf11e06af710"
sum="a1a8658fb645764ad38241ce182e9b8a"
proved="true"
expanded="true"
shape="preconditionainfix <V2V0Aainfix <=V5V2Aainfix <=c0V5Iapermut_subV6V7V1ainfix +V2c1Iasorted_subV7V1ainfix +V4c1Aapermut_subV6V7V1ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V1V4Aainfix <=c0V1Iainfix >=agetV6V9V8Iainfix <=V9V2Aainfix <=V5V9FAainfix =agetV6V10V8Iainfix <V10V5Aainfix <V4V10FAainfix <=agetV6V11V8Iainfix <=V11V4Aainfix <=V1V11FEAapermut_subV3V6V1ainfix +V2c1Aainfix <=V5V2Aainfix <V4V5Aainfix <=V1V4Aainfix <=c0V0FIainfix <V2V0Aainfix <V1V2Aainfix <=c0V1Iainfix <V1V2Iainfix <V2V0Aainfix <=V1V2Aainfix <=c0V1Aainfix <=c0V0FF">
......@@ -163,7 +163,7 @@
locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19"
expl="7. assertion"
sum="ffc073f16103d696d99568ec5ba9f74a"
sum="d4c5f783e016831c9b4150a9a837996b"
proved="true"
expanded="true"
shape="assertionapermut_subV7V8V1ainfix +V2c1Iasorted_subV8V5ainfix +V2c1Aapermut_subV7V8V5ainfix +V2c1Aainfix <=c0V0FIainfix <V2V0Aainfix <=V5V2Aainfix <=c0V5Iapermut_subV6V7V1ainfix +V2c1Iasorted_subV7V1ainfix +V4c1Aapermut_subV6V7V1ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V1V4Aainfix <=c0V1Iainfix >=agetV6V10V9Iainfix <=V10V2Aainfix <=V5V10FAainfix =agetV6V11V9Iainfix <V11V5Aainfix <V4V11FAainfix <=agetV6V12V9Iainfix <=V12V4Aainfix <=V1V12FEAapermut_subV3V6V1ainfix +V2c1Aainfix <=V5V2Aainfix <V4V5Aainfix <=V1V4Aainfix <=c0V0FIainfix <V2V0Aainfix <V1V2Aainfix <=c0V1Iainfix <V1V2Iainfix <V2V0Aainfix <=V1V2Aainfix <=c0V1Aainfix <=c0V0FF">
......@@ -183,7 +183,7 @@
locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19"
expl="8. postcondition"
sum="08fdd2672d24fafbe0f05ee5f635f6e9"
sum="7b2272981678c505d00d003541a25323"
proved="true"
expanded="true"
shape="postconditionapermut_subV3V8V1ainfix +V2c1Iapermut_subV7V8V1ainfix +V2c1Iasorted_subV8V5ainfix +V2c1Aapermut_subV7V8V5ainfix +V2c1Aainfix <=c0V0FIainfix <V2V0Aainfix <=V5V2Aainfix <=c0V5Iapermut_subV6V7V1ainfix +V2c1Iasorted_subV7V1ainfix +V4c1Aapermut_subV6V7V1ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V1V4Aainfix <=c0V1Iainfix >=agetV6V10V9Iainfix <=V10V2Aainfix <=V5V10FAainfix =agetV6V11V9Iainfix <V11V5Aainfix <V4V11FAainfix <=agetV6V12V9Iainfix <=V12V4Aainfix <=V1V12FEAapermut_subV3V6V1ainfix +V2c1Aainfix <=V5V2Aainfix <V4V5Aainfix <=V1V4Aainfix <=c0V0FIainfix <V2V0Aainfix <V1V2Aainfix <=c0V1Iainfix <V1V2Iainfix <V2V0Aainfix <=V1V2Aainfix <=c0V1Aainfix <=c0V0FF">
......@@ -203,7 +203,7 @@
locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19"
expl="9. postcondition"
sum="35ebeae2f5fbe5224561cff570ab23b9"
sum="39cbb1c21ab896a97d894567ed414a90"
proved="true"
expanded="true"
shape="postconditionasorted_subV8V1ainfix +V2c1Iapermut_subV7V8V1ainfix +V2c1Iasorted_subV8V5ainfix +V2c1Aapermut_subV7V8V5ainfix +V2c1Aainfix <=c0V0FIainfix <V2V0Aainfix <=V5V2Aainfix <=c0V5Iapermut_subV6V7V1ainfix +V2c1Iasorted_subV7V1ainfix +V4c1Aapermut_subV6V7V1ainfix +V4c1Aainfix <=c0V0FIainfix <V4V0Aainfix <=V1V4Aainfix <=c0V1Iainfix >=agetV6V10V9Iainfix <=V10V2Aainfix <=V5V10FAainfix =agetV6V11V9Iainfix <V11V5Aainfix <V4V11FAainfix <=agetV6V12V9Iainfix <=V12V4Aainfix <=V1V12FEAapermut_subV3V6V1ainfix +V2c1Aainfix <=V5V2Aainfix <V4V5Aainfix <=V1V4Aainfix <=c0V0FIainfix <V2V0Aainfix <V1V2Aainfix <=c0V1Iainfix <V1V2Iainfix <V2V0Aainfix <=V1V2Aainfix <=c0V1Aainfix <=c0V0FF">
......@@ -223,7 +223,7 @@
memlimit="1000"
obsolete="false"
archived="false">
<result status="valid" time="36.92"/>
<result status="valid" time="16.52"/>
</proof>
</goal>
<goal
......@@ -231,7 +231,7 @@
locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19"
expl="10. postcondition"
sum="e6bf165a8862cc0215e1fe933570e6fe"
sum="c9aee77b1de0f789e80a8d6207e238a8"
proved="true"
expanded="true"
shape="postconditionapermut_subV3V3V1ainfix +V2c1INainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -251,7 +251,7 @@
locfile="../algo64.mlw"
loclnum="37" loccnumb="10" loccnume="19"
expl="11. postcondition"
sum="07f6b005264964017be91678f79e1b36"
sum="324cbdea9c2d639c2179bcbffb508f78"
proved="true"
expanded="true"
shape="postconditionasorted_subV3V1ainfix +V2c1INainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V1V2Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......
......@@ -24,7 +24,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="VC for find"
sum="2f16b3d0d2ffa33ade70215412e83ac6"
sum="67ec55c3ccc180a1f86f195faf1363fa"
proved="true"
expanded="true"
shape="iainfix &lt;=agetV4V3agetV4V5Iainfix &lt;=V5V2Aainfix &lt;=V3V5FAainfix &lt;=agetV4V6agetV4V3Iainfix &lt;=V6V3Aainfix &lt;=V1V6FAapermut_subV4V4V1ainfix +V2c1iiainfix &lt;=agetV9V3agetV9V10Iainfix &lt;=V10V2Aainfix &lt;=V3V10FAainfix &lt;=agetV9V11agetV9V3Iainfix &lt;=V11V3Aainfix &lt;=V1V11FAapermut_subV4V9V1ainfix +V2c1ainfix &lt;=agetV12V3agetV12V13Iainfix &lt;=V13V2Aainfix &lt;=V3V13FAainfix &lt;=agetV12V14agetV12V3Iainfix &lt;=V14V3Aainfix &lt;=V1V14FAapermut_subV4V12V1ainfix +V2c1Iainfix &lt;=agetV12V3agetV12V15Iainfix &lt;=V15V2Aainfix &lt;=V3V15FAainfix &lt;=agetV12V16agetV12V3Iainfix &lt;=V16V3Aainfix &lt;=V8V16FAapermut_subV9V12V8ainfix +V2c1Aainfix &lt;=c0V0FAainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V8V3Aainfix &lt;=c0V8Aainfix &lt;ainfix -V2V8ainfix -V2V1Aainfix &lt;=c0ainfix -V2V1ainfix &lt;=V8V3Aapermut_subV9V9V1ainfix +V2c1iainfix &lt;=agetV17V3agetV17V18Iainfix &lt;=V18V2Aainfix &lt;=V3V18FAainfix &lt;=agetV17V19agetV17V3Iainfix &lt;=V19V3Aainfix &lt;=V1V19FAapermut_subV4V17V1ainfix +V2c1ainfix &lt;=agetV20V3agetV20V21Iainfix &lt;=V21V2Aainfix &lt;=V3V21FAainfix &lt;=agetV20V22agetV20V3Iainfix &lt;=V22V3Aainfix &lt;=V1V22FAapermut_subV4V20V1ainfix +V2c1Iainfix &lt;=agetV20V3agetV20V23Iainfix &lt;=V23V2Aainfix &lt;=V3V23FAainfix &lt;=agetV20V24agetV20V3Iainfix &lt;=V24V3Aainfix &lt;=V8V24FAapermut_subV17V20V8ainfix +V2c1Aainfix &lt;=c0V0FAainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V8V3Aainfix &lt;=c0V8Aainfix &lt;ainfix -V2V8ainfix -V2V1Aainfix &lt;=c0ainfix -V2V1ainfix &lt;=V8V3Aapermut_subV9V17V1ainfix +V2c1Iainfix &lt;=agetV17V3agetV17V25Iainfix &lt;=V25V7Aainfix &lt;=V3V25FAainfix &lt;=agetV17V26agetV17V3Iainfix &lt;=V26V3Aainfix &lt;=V1V26FAapermut_subV9V17V1ainfix +V7c1Aainfix &lt;=c0V0FAainfix &lt;V7V0Aainfix &lt;=V3V7Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;ainfix -V7V1ainfix -V2V1Aainfix &lt;=c0ainfix -V2V1ainfix &lt;=V3V7Aapermut_subV4V9V1ainfix +V2c1Iainfix &gt;=agetV9V28V27Iainfix &lt;=V28V2Aainfix &lt;=V8V28FAainfix =agetV9V29V27Iainfix &lt;V29V8Aainfix &lt;V7V29FAainfix &lt;=agetV9V30V27Iainfix &lt;=V30V7Aainfix &lt;=V1V30FEAapermut_subV4V9V1ainfix +V2c1Aainfix &lt;=V8V2Aainfix &lt;V7V8Aainfix &lt;=V1V7Aainfix &lt;=c0V0FAainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1ainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -39,7 +39,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="1. precondition"
sum="7d0873ea598c2e785c61aa2be0bef1ff"
sum="a701737147d0f077fd56174d263855c3"
proved="true"
expanded="true"
shape="preconditionainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -59,7 +59,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="2. assertion"
sum="2bf5ce653491cfc69af3a6073d20ed6d"
sum="5ed8046deddc569bd0dffd402fa4b10d"
proved="true"
expanded="true"
shape="assertionapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V9V8Iainfix &lt;=V9V2Aainfix &lt;=V6V9FAainfix =agetV7V10V8Iainfix &lt;V10V6Aainfix &lt;V5V10FAainfix &lt;=agetV7V11V8Iainfix &lt;=V11V5Aainfix &lt;=V1V11FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -79,7 +79,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="3. variant decrease"
sum="81dd1eadf8dd7c688e69da85750833de"
sum="2e4287997a1c330eb7a2384e720e6e91"
proved="true"
expanded="true"
shape="variant decreaseainfix &lt;ainfix -V5V1ainfix -V2V1Aainfix &lt;=c0ainfix -V2V1Iainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V9V8Iainfix &lt;=V9V2Aainfix &lt;=V6V9FAainfix =agetV7V10V8Iainfix &lt;V10V6Aainfix &lt;V5V10FAainfix &lt;=agetV7V11V8Iainfix &lt;=V11V5Aainfix &lt;=V1V11FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -99,7 +99,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="4. precondition"
sum="24e2e31007423654fb00c31512b19d05"
sum="1b75e0b82b9716bd373d71411a75e3aa"
proved="true"
expanded="true"
shape="preconditionainfix &lt;V5V0Aainfix &lt;=V3V5Aainfix &lt;=V1V3Aainfix &lt;=c0V1Iainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V9V8Iainfix &lt;=V9V2Aainfix &lt;=V6V9FAainfix =agetV7V10V8Iainfix &lt;V10V6Aainfix &lt;V5V10FAainfix &lt;=agetV7V11V8Iainfix &lt;=V11V5Aainfix &lt;=V1V11FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -119,7 +119,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="5. assertion"
sum="93c57680031c2a172dbaae261247a58f"
sum="de395bcd8d4f60f9ef9815c77f7d017e"
proved="true"
expanded="true"
shape="assertionapermut_subV7V8V1ainfix +V2c1Iainfix &lt;=agetV8V3agetV8V9Iainfix &lt;=V9V5Aainfix &lt;=V3V9FAainfix &lt;=agetV8V10agetV8V3Iainfix &lt;=V10V3Aainfix &lt;=V1V10FAapermut_subV7V8V1ainfix +V5c1Aainfix &lt;=c0V0FIainfix &lt;V5V0Aainfix &lt;=V3V5Aainfix &lt;=V1V3Aainfix &lt;=c0V1Iainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V12V11Iainfix &lt;=V12V2Aainfix &lt;=V6V12FAainfix =agetV7V13V11Iainfix &lt;V13V6Aainfix &lt;V5V13FAainfix &lt;=agetV7V14V11Iainfix &lt;=V14V5Aainfix &lt;=V1V14FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -139,7 +139,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="6. variant decrease"
sum="dc59342bfb6c6fce4f0503f54ae28a65"
sum="c3966fd69d450ac9930afd9e882d87e7"
proved="true"
expanded="true"
shape="variant decreaseainfix &lt;ainfix -V2V6ainfix -V2V1Aainfix &lt;=c0ainfix -V2V1Iainfix &lt;=V6V3Iapermut_subV7V8V1ainfix +V2c1Iainfix &lt;=agetV8V3agetV8V9Iainfix &lt;=V9V5Aainfix &lt;=V3V9FAainfix &lt;=agetV8V10agetV8V3Iainfix &lt;=V10V3Aainfix &lt;=V1V10FAapermut_subV7V8V1ainfix +V5c1Aainfix &lt;=c0V0FIainfix &lt;V5V0Aainfix &lt;=V3V5Aainfix &lt;=V1V3Aainfix &lt;=c0V1Iainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V12V11Iainfix &lt;=V12V2Aainfix &lt;=V6V12FAainfix =agetV7V13V11Iainfix &lt;V13V6Aainfix &lt;V5V13FAainfix &lt;=agetV7V14V11Iainfix &lt;=V14V5Aainfix &lt;=V1V14FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -159,7 +159,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="7. precondition"
sum="36b82eecf06cab97189bf4a65be40fc3"
sum="af90567dab9ebcbca6840306dcdb519e"
proved="true"
expanded="true"
shape="preconditionainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V6V3Aainfix &lt;=c0V6Iainfix &lt;=V6V3Iapermut_subV7V8V1ainfix +V2c1Iainfix &lt;=agetV8V3agetV8V9Iainfix &lt;=V9V5Aainfix &lt;=V3V9FAainfix &lt;=agetV8V10agetV8V3Iainfix &lt;=V10V3Aainfix &lt;=V1V10FAapermut_subV7V8V1ainfix +V5c1Aainfix &lt;=c0V0FIainfix &lt;V5V0Aainfix &lt;=V3V5Aainfix &lt;=V1V3Aainfix &lt;=c0V1Iainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V12V11Iainfix &lt;=V12V2Aainfix &lt;=V6V12FAainfix =agetV7V13V11Iainfix &lt;V13V6Aainfix &lt;V5V13FAainfix &lt;=agetV7V14V11Iainfix &lt;=V14V5Aainfix &lt;=V1V14FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -179,7 +179,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="8. postcondition"
sum="07e508b5616f45966550b2f25105a314"
sum="7b2db9ca49e6fb8ee1a87074ac654d5a"
proved="true"
expanded="true"
shape="postconditionapermut_subV4V9V1ainfix +V2c1Iainfix &lt;=agetV9V3agetV9V10Iainfix &lt;=V10V2Aainfix &lt;=V3V10FAainfix &lt;=agetV9V11agetV9V3Iainfix &lt;=V11V3Aainfix &lt;=V6V11FAapermut_subV8V9V6ainfix +V2c1Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V6V3Aainfix &lt;=c0V6Iainfix &lt;=V6V3Iapermut_subV7V8V1ainfix +V2c1Iainfix &lt;=agetV8V3agetV8V12Iainfix &lt;=V12V5Aainfix &lt;=V3V12FAainfix &lt;=agetV8V13agetV8V3Iainfix &lt;=V13V3Aainfix &lt;=V1V13FAapermut_subV7V8V1ainfix +V5c1Aainfix &lt;=c0V0FIainfix &lt;V5V0Aainfix &lt;=V3V5Aainfix &lt;=V1V3Aainfix &lt;=c0V1Iainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V15V14Iainfix &lt;=V15V2Aainfix &lt;=V6V15FAainfix =agetV7V16V14Iainfix &lt;V16V6Aainfix &lt;V5V16FAainfix &lt;=agetV7V17V14Iainfix &lt;=V17V5Aainfix &lt;=V1V17FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -199,7 +199,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="9. postcondition"
sum="162ae67c50703670ff2a1ea996a0bc36"
sum="030d0640a022c2f334414fc71ce5c29b"
proved="true"
expanded="true"
shape="postconditionainfix &lt;=agetV9V10agetV9V3Iainfix &lt;=V10V3Aainfix &lt;=V1V10FIainfix &lt;=agetV9V3agetV9V11Iainfix &lt;=V11V2Aainfix &lt;=V3V11FAainfix &lt;=agetV9V12agetV9V3Iainfix &lt;=V12V3Aainfix &lt;=V6V12FAapermut_subV8V9V6ainfix +V2c1Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V6V3Aainfix &lt;=c0V6Iainfix &lt;=V6V3Iapermut_subV7V8V1ainfix +V2c1Iainfix &lt;=agetV8V3agetV8V13Iainfix &lt;=V13V5Aainfix &lt;=V3V13FAainfix &lt;=agetV8V14agetV8V3Iainfix &lt;=V14V3Aainfix &lt;=V1V14FAapermut_subV7V8V1ainfix +V5c1Aainfix &lt;=c0V0FIainfix &lt;V5V0Aainfix &lt;=V3V5Aainfix &lt;=V1V3Aainfix &lt;=c0V1Iainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V16V15Iainfix &lt;=V16V2Aainfix &lt;=V6V16FAainfix =agetV7V17V15Iainfix &lt;V17V6Aainfix &lt;V5V17FAainfix &lt;=agetV7V18V15Iainfix &lt;=V18V5Aainfix &lt;=V1V18FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -219,7 +219,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="10. postcondition"
sum="24a71732828a2f8a23e0039b2967d33e"
sum="31325f02c9143bf7f4de39348d0369f6"
proved="true"
expanded="true"
shape="postconditionainfix &lt;=agetV9V3agetV9V10Iainfix &lt;=V10V2Aainfix &lt;=V3V10FIainfix &lt;=agetV9V3agetV9V11Iainfix &lt;=V11V2Aainfix &lt;=V3V11FAainfix &lt;=agetV9V12agetV9V3Iainfix &lt;=V12V3Aainfix &lt;=V6V12FAapermut_subV8V9V6ainfix +V2c1Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V6V3Aainfix &lt;=c0V6Iainfix &lt;=V6V3Iapermut_subV7V8V1ainfix +V2c1Iainfix &lt;=agetV8V3agetV8V13Iainfix &lt;=V13V5Aainfix &lt;=V3V13FAainfix &lt;=agetV8V14agetV8V3Iainfix &lt;=V14V3Aainfix &lt;=V1V14FAapermut_subV7V8V1ainfix +V5c1Aainfix &lt;=c0V0FIainfix &lt;V5V0Aainfix &lt;=V3V5Aainfix &lt;=V1V3Aainfix &lt;=c0V1Iainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V16V15Iainfix &lt;=V16V2Aainfix &lt;=V6V16FAainfix =agetV7V17V15Iainfix &lt;V17V6Aainfix &lt;V5V17FAainfix &lt;=agetV7V18V15Iainfix &lt;=V18V5Aainfix &lt;=V1V18FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -239,7 +239,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="11. postcondition"
sum="95ae44f79101954b3364c197b3476463"
sum="36a400390503c6d39332b490b1c3fecd"
proved="true"
expanded="true"
shape="postconditionapermut_subV4V8V1ainfix +V2c1INainfix &lt;=V6V3Iapermut_subV7V8V1ainfix +V2c1Iainfix &lt;=agetV8V3agetV8V9Iainfix &lt;=V9V5Aainfix &lt;=V3V9FAainfix &lt;=agetV8V10agetV8V3Iainfix &lt;=V10V3Aainfix &lt;=V1V10FAapermut_subV7V8V1ainfix +V5c1Aainfix &lt;=c0V0FIainfix &lt;V5V0Aainfix &lt;=V3V5Aainfix &lt;=V1V3Aainfix &lt;=c0V1Iainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V12V11Iainfix &lt;=V12V2Aainfix &lt;=V6V12FAainfix =agetV7V13V11Iainfix &lt;V13V6Aainfix &lt;V5V13FAainfix &lt;=agetV7V14V11Iainfix &lt;=V14V5Aainfix &lt;=V1V14FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -259,7 +259,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="12. postcondition"
sum="95626d86a40ee76695393d609ffb8396"
sum="37bec2d5e62be3affd6db285c2fd958b"
proved="true"
expanded="true"
shape="postconditionainfix &lt;=agetV8V9agetV8V3Iainfix &lt;=V9V3Aainfix &lt;=V1V9FINainfix &lt;=V6V3Iapermut_subV7V8V1ainfix +V2c1Iainfix &lt;=agetV8V3agetV8V10Iainfix &lt;=V10V5Aainfix &lt;=V3V10FAainfix &lt;=agetV8V11agetV8V3Iainfix &lt;=V11V3Aainfix &lt;=V1V11FAapermut_subV7V8V1ainfix +V5c1Aainfix &lt;=c0V0FIainfix &lt;V5V0Aainfix &lt;=V3V5Aainfix &lt;=V1V3Aainfix &lt;=c0V1Iainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V13V12Iainfix &lt;=V13V2Aainfix &lt;=V6V13FAainfix =agetV7V14V12Iainfix &lt;V14V6Aainfix &lt;V5V14FAainfix &lt;=agetV7V15V12Iainfix &lt;=V15V5Aainfix &lt;=V1V15FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -279,7 +279,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="13. postcondition"
sum="a26ea7c31a382ef7bf7c5a2219de4ad0"
sum="03e2a09eaeb2591a301f3ec186ebeb3b"
proved="true"
expanded="true"
shape="postconditionainfix &lt;=agetV8V3agetV8V9Iainfix &lt;=V9V2Aainfix &lt;=V3V9FINainfix &lt;=V6V3Iapermut_subV7V8V1ainfix +V2c1Iainfix &lt;=agetV8V3agetV8V10Iainfix &lt;=V10V5Aainfix &lt;=V3V10FAainfix &lt;=agetV8V11agetV8V3Iainfix &lt;=V11V3Aainfix &lt;=V1V11FAapermut_subV7V8V1ainfix +V5c1Aainfix &lt;=c0V0FIainfix &lt;V5V0Aainfix &lt;=V3V5Aainfix &lt;=V1V3Aainfix &lt;=c0V1Iainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V13V12Iainfix &lt;=V13V2Aainfix &lt;=V6V13FAainfix =agetV7V14V12Iainfix &lt;V14V6Aainfix &lt;V5V14FAainfix &lt;=agetV7V15V12Iainfix &lt;=V15V5Aainfix &lt;=V1V15FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -299,7 +299,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="14. assertion"
sum="3888f72a70709fd30411c0456e3a7078"
sum="1ae084decfcae2fc0721d34fe7d89450"
proved="true"
expanded="true"
shape="assertionapermut_subV7V7V1ainfix +V2c1INainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V9V8Iainfix &lt;=V9V2Aainfix &lt;=V6V9FAainfix =agetV7V10V8Iainfix &lt;V10V6Aainfix &lt;V5V10FAainfix &lt;=agetV7V11V8Iainfix &lt;=V11V5Aainfix &lt;=V1V11FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -319,7 +319,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="15. variant decrease"
sum="8f75b8feec266e117a415c045a8a73b8"
sum="cdfd489d81c34447b303d314a8688864"
proved="true"
expanded="true"
shape="variant decreaseainfix &lt;ainfix -V2V6ainfix -V2V1Aainfix &lt;=c0ainfix -V2V1Iainfix &lt;=V6V3Iapermut_subV7V7V1ainfix +V2c1INainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V9V8Iainfix &lt;=V9V2Aainfix &lt;=V6V9FAainfix =agetV7V10V8Iainfix &lt;V10V6Aainfix &lt;V5V10FAainfix &lt;=agetV7V11V8Iainfix &lt;=V11V5Aainfix &lt;=V1V11FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -339,7 +339,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="16. precondition"
sum="af1ab5e0c7638720b448dd4d9a340ddb"
sum="f6f42ffaea011aa23e0a7a69a849db71"
proved="true"
expanded="true"
shape="preconditionainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V6V3Aainfix &lt;=c0V6Iainfix &lt;=V6V3Iapermut_subV7V7V1ainfix +V2c1INainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V9V8Iainfix &lt;=V9V2Aainfix &lt;=V6V9FAainfix =agetV7V10V8Iainfix &lt;V10V6Aainfix &lt;V5V10FAainfix &lt;=agetV7V11V8Iainfix &lt;=V11V5Aainfix &lt;=V1V11FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -359,7 +359,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="17. postcondition"
sum="485100115d0eaf1f3ebd5d61a540183e"
sum="bdcfb84d8ce110a4e4925b0fc2ca2dd2"
proved="true"
expanded="true"
shape="postconditionapermut_subV4V8V1ainfix +V2c1Iainfix &lt;=agetV8V3agetV8V9Iainfix &lt;=V9V2Aainfix &lt;=V3V9FAainfix &lt;=agetV8V10agetV8V3Iainfix &lt;=V10V3Aainfix &lt;=V6V10FAapermut_subV7V8V6ainfix +V2c1Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V6V3Aainfix &lt;=c0V6Iainfix &lt;=V6V3Iapermut_subV7V7V1ainfix +V2c1INainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V12V11Iainfix &lt;=V12V2Aainfix &lt;=V6V12FAainfix =agetV7V13V11Iainfix &lt;V13V6Aainfix &lt;V5V13FAainfix &lt;=agetV7V14V11Iainfix &lt;=V14V5Aainfix &lt;=V1V14FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -379,7 +379,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="18. postcondition"
sum="e9230852b13e066ac0b6d7b5132fa821"
sum="e46132288325392a1577fa5ecbb4f6b9"
proved="true"
expanded="true"
shape="postconditionainfix &lt;=agetV8V9agetV8V3Iainfix &lt;=V9V3Aainfix &lt;=V1V9FIainfix &lt;=agetV8V3agetV8V10Iainfix &lt;=V10V2Aainfix &lt;=V3V10FAainfix &lt;=agetV8V11agetV8V3Iainfix &lt;=V11V3Aainfix &lt;=V6V11FAapermut_subV7V8V6ainfix +V2c1Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V6V3Aainfix &lt;=c0V6Iainfix &lt;=V6V3Iapermut_subV7V7V1ainfix +V2c1INainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V13V12Iainfix &lt;=V13V2Aainfix &lt;=V6V13FAainfix =agetV7V14V12Iainfix &lt;V14V6Aainfix &lt;V5V14FAainfix &lt;=agetV7V15V12Iainfix &lt;=V15V5Aainfix &lt;=V1V15FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -399,7 +399,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="19. postcondition"
sum="686b774a4775e14061b99bc546cf9b85"
sum="3c32281901cf5fc12858478da7320408"
proved="true"
expanded="true"
shape="postconditionainfix &lt;=agetV8V3agetV8V9Iainfix &lt;=V9V2Aainfix &lt;=V3V9FIainfix &lt;=agetV8V3agetV8V10Iainfix &lt;=V10V2Aainfix &lt;=V3V10FAainfix &lt;=agetV8V11agetV8V3Iainfix &lt;=V11V3Aainfix &lt;=V6V11FAapermut_subV7V8V6ainfix +V2c1Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V6V3Aainfix &lt;=c0V6Iainfix &lt;=V6V3Iapermut_subV7V7V1ainfix +V2c1INainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V13V12Iainfix &lt;=V13V2Aainfix &lt;=V6V13FAainfix =agetV7V14V12Iainfix &lt;V14V6Aainfix &lt;V5V14FAainfix &lt;=agetV7V15V12Iainfix &lt;=V15V5Aainfix &lt;=V1V15FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -419,7 +419,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="20. postcondition"
sum="3491cfb9f550a2590716080f3405c9ad"
sum="667cd3c001e9f470e4e0a2c05f61bd06"
proved="true"
expanded="true"
shape="postconditionapermut_subV4V7V1ainfix +V2c1INainfix &lt;=V6V3Iapermut_subV7V7V1ainfix +V2c1INainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V9V8Iainfix &lt;=V9V2Aainfix &lt;=V6V9FAainfix =agetV7V10V8Iainfix &lt;V10V6Aainfix &lt;V5V10FAainfix &lt;=agetV7V11V8Iainfix &lt;=V11V5Aainfix &lt;=V1V11FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -439,7 +439,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="21. postcondition"
sum="be86130e9701ff5035caf7677d68d7d0"
sum="9f3392dcd10740972d87bd820f608221"
proved="true"
expanded="true"
shape="postconditionainfix &lt;=agetV7V8agetV7V3Iainfix &lt;=V8V3Aainfix &lt;=V1V8FINainfix &lt;=V6V3Iapermut_subV7V7V1ainfix +V2c1INainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V10V9Iainfix &lt;=V10V2Aainfix &lt;=V6V10FAainfix =agetV7V11V9Iainfix &lt;V11V6Aainfix &lt;V5V11FAainfix &lt;=agetV7V12V9Iainfix &lt;=V12V5Aainfix &lt;=V1V12FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -459,7 +459,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="22. postcondition"
sum="d264f0bd66b5e50da59290f41c019112"
sum="210eac54ba42e792b65bafd783af45d0"
proved="true"
expanded="true"
shape="postconditionainfix &lt;=agetV7V3agetV7V8Iainfix &lt;=V8V2Aainfix &lt;=V3V8FINainfix &lt;=V6V3Iapermut_subV7V7V1ainfix +V2c1INainfix &lt;=V3V5Iapermut_subV4V7V1ainfix +V2c1Iainfix &gt;=agetV7V10V9Iainfix &lt;=V10V2Aainfix &lt;=V6V10FAainfix =agetV7V11V9Iainfix &lt;V11V6Aainfix &lt;V5V11FAainfix &lt;=agetV7V12V9Iainfix &lt;=V12V5Aainfix &lt;=V1V12FEAapermut_subV4V7V1ainfix +V2c1Aainfix &lt;=V6V2Aainfix &lt;V5V6Aainfix &lt;=V1V5Aainfix &lt;=c0V0FIainfix &lt;V2V0Aainfix &lt;V1V2Aainfix &lt;=c0V1Iainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -479,7 +479,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="23. postcondition"
sum="47c16f4c3582792f61d00df85c7f56ec"
sum="e0d1bc3bcf5338ea077594f79141c269"
proved="true"
expanded="true"
shape="postconditionapermut_subV4V4V1ainfix +V2c1INainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -499,7 +499,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="24. postcondition"
sum="40e2b5e0869b11f00f97350d270a25c7"
sum="dacd350857918fa57e5b873507038e20"
proved="true"
expanded="true"
shape="postconditionainfix &lt;=agetV4V5agetV4V3Iainfix &lt;=V5V3Aainfix &lt;=V1V5FINainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......@@ -519,7 +519,7 @@
locfile="../algo65.mlw"
loclnum="36" loccnumb="10" loccnume="14"
expl="25. postcondition"
sum="87d4967c990bbc95b32d6ff616e1e732"
sum="bfe6087eae0c5f6900a5776da7d91c91"
proved="true"
expanded="true"
shape="postconditionainfix &lt;=agetV4V3agetV4V5Iainfix &lt;=V5V2Aainfix &lt;=V3V5FINainfix &lt;V1V2Iainfix &lt;V2V0Aainfix &lt;=V3V2Aainfix &lt;=V1V3Aainfix &lt;=c0V1Aainfix &lt;=c0V0FF">
......
......@@ -43,7 +43,7 @@
name="Test"
locfile="../alphaBeta.mlw"
loclnum="76" loccnumb="7" loccnume="11"
sum="b97508a5e6364636f5f02cfc58030f63"
sum="f66146e79e082693b350edcf7f60f0d8"
proved="true"
expanded="false"
shape="ainfix &lt;=aprefix -aposition_valueado_moveV0V1aminmaxV0c1IamemV1V2Lalegal_movesV0F">
......@@ -70,14 +70,14 @@
memlimit="1000"
obsolete="false"
archived="false">
<result status="valid" time="0.19"/>
<result status="valid" time="0.02"/>
</proof>
</goal>
<goal
name="minmax_bound"
locfile="../alphaBeta.mlw"
loclnum="82" loccnumb="8" loccnume="20"
sum="bbb697c0cfcf19abc3fbd55aee2bf562"
sum="5e94a9518279472d5a187393a326ef9f"
proved="true"
expanded="false"
shape="ainfix &lt;aminmaxV0V1ainfinityAainfix &lt;aprefix -ainfinityaminmaxV0V1Iainfix &gt;=V1c0F">
......@@ -95,7 +95,7 @@
name="minmax_nomove"
locfile="../alphaBeta.mlw"
loclnum="86" loccnumb="8" loccnume="21"
sum="0d8cf238d83e205510be29542efe826b"
sum="4d403af107fd8fb5aaf11c0a5e886a5f"
proved="true"
expanded="false"
shape="ainfix =aminmaxV0V1aposition_valueV0Iainfix =alegal_movesV0aNilAainfix &gt;=V1c0F">
......@@ -160,7 +160,7 @@
locfile="../alphaBeta.mlw"
loclnum="109" loccnumb="10" loccnume="31"
expl="VC for move_value_alpha_beta"
sum="b293a359249fd530e078d35691f1fdb3"
sum="3019c70efe72aeccd36f2abd4f9508d8"
proved="true"
expanded="false"
shape="iiainfix &lt;=V10V0ainfix &gt;=V10V1ainfix &lt;=V11aprefix -V1ainfix =V10aprefix -V11ainfix &lt;V11aprefix -V0Aainfix &lt;aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix &gt;=V9V7ainfix &lt;=V9V8ainfix &lt;=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix &lt;aminmaxV5V6V7Aainfix &lt;V8aminmaxV5V6FAainfix &gt;=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix &gt;=V3c1F">
......@@ -175,7 +175,7 @@
locfile="../alphaBeta.mlw"
loclnum="109" loccnumb="10" loccnume="31"
expl="1. precondition"
sum="fc02b5563aad2dbdf7d3d9058d13f62c"
sum="844fd2ef9205b3f4c098e9dd71e617b9"
proved="true"
expanded="false"
shape="preconditionainfix &gt;=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix &gt;=V3c1F">
......@@ -235,7 +235,7 @@
locfile="../alphaBeta.mlw"
loclnum="109" loccnumb="10" loccnume="31"
expl="2. postcondition"
sum="762aee9d06bb39d1023e5c19b8e3bcba"
sum="085f6aac34de83587f9f539445a78ebc"
proved="true"
expanded="false"
shape="postconditioniiainfix &lt;=V10V0ainfix &gt;=V10V1ainfix &lt;=V11aprefix -V1ainfix =V10aprefix -V11ainfix &lt;V11aprefix -V0Aainfix &lt;aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix &gt;=V9V7ainfix &lt;=V9V8ainfix &lt;=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix &lt;aminmaxV5V6V7Aainfix &lt;V8aminmaxV5V6FIainfix &gt;=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix &gt;=V3c1F">
......@@ -250,7 +250,7 @@
locfile="../alphaBeta.mlw"
loclnum="109" loccnumb="10" loccnume="31"
expl="1. postcondition"
sum="db3f91a0a59f552158d7a7a1b3612828"
sum="896507065c99ea0ee97d8e13dd5e6019"
proved="true"
expanded="false"
shape="postconditionainfix =V10aprefix -V11Iainfix &lt;V11aprefix -V0Aainfix &lt;aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix &gt;=V9V7ainfix &lt;=V9V8ainfix &lt;=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix &lt;aminmaxV5V6V7Aainfix &lt;V8aminmaxV5V6FIainfix &gt;=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix &gt;=V3c1F">
......@@ -270,7 +270,7 @@
locfile="../alphaBeta.mlw"
loclnum="109" loccnumb="10" loccnume="31"
expl="2. postcondition"
sum="ee0d767f383db49077ea9b1cbe5a3181"
sum="b4035a89477ec6c3cc9f18677a311552"
proved="true"
expanded="false"
shape="postconditionainfix &gt;=V10V1Iainfix &lt;=V11aprefix -V1INainfix &lt;V11aprefix -V0Aainfix &lt;aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix &gt;=V9V7ainfix &lt;=V9V8ainfix &lt;=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix &lt;aminmaxV5V6V7Aainfix &lt;V8aminmaxV5V6FIainfix &gt;=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix &gt;=V3c1F">
......@@ -290,7 +290,7 @@
locfile="../alphaBeta.mlw"
loclnum="109" loccnumb="10" loccnume="31"
expl="3. postcondition"
sum="e995f931a6f654b51b82bb0ee88a642e"
sum="4483f965602c51f2bb7151bd18b692d1"
proved="true"
expanded="false"
shape="postconditionainfix &lt;=V10V0INainfix &lt;=V11aprefix -V1INainfix &lt;V11aprefix -V0Aainfix &lt;aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiiainfix &gt;=V9V7ainfix &lt;=V9V8ainfix &lt;=aminmaxV5V6V8ainfix =V9aminmaxV5V6ainfix &lt;aminmaxV5V6V7Aainfix &lt;V8aminmaxV5V6FIainfix &gt;=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix &gt;=V3c1F">
......@@ -314,7 +314,7 @@
locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15"
expl="VC for negabeta"
sum="ffca5ea3e66e79f4b33682b603d00068"
sum="10b003198bf762bdc66fa147058ba6ad"
proved="false"
expanded="true"
shape="iCiiainfix &gt;=V4V1ainfix &lt;=V4V0ainfix &lt;=aminmaxV2V3V0ainfix =V4aminmaxV2V3ainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Laposition_valueV2aNiliiiainfix &gt;=V9V1ainfix &lt;=V9V0ainfix &lt;=aminmaxV2V3V0ainfix =V9aminmaxV2V3ainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Iiiiainfix &gt;=V9V1ainfix &lt;=V9V8ainfix &lt;=V11V8ainfix =V9V11ainfix &lt;V11V1Aainfix &lt;V8V11LaminaTuple2V2V3V10ainfix =V9V7ais_emptyV10LaelementsV6FAainfix &gt;=V3c1LamaxV7V0iiainfix &gt;=V7V1ainfix &lt;=V7V0ainfix &lt;=aminmaxV2V3V0ainfix =V7aminmaxV2V3ainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix &gt;=V7V1Iiiainfix &lt;=V7V0ainfix &gt;=V7V1ainfix &lt;=V12aprefix -V1ainfix =V7aprefix -V12ainfix &lt;V12aprefix -V0Aainfix &lt;aprefix -V1V12Laminmaxado_moveV2V5ainfix -V3c1FAainfix &gt;=V3c1aConsVValegal_movesV2iiainfix &gt;=V13V1ainfix &lt;=V13V0ainfix &lt;=aminmaxV2V3V0ainfix =V13aminmaxV2V3ainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Laposition_valueV2ainfix =V3c0Iainfix &gt;=V3c0F">
......@@ -329,7 +329,7 @@
locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15"
expl="1. postcondition"
sum="f7ca4d3c20c4042ba2e1ed4718a03299"
sum="89e59e502c4e02f20fb7311ec0a088fe"
proved="true"
expanded="false"
shape="postconditioniiainfix &gt;=V4V1ainfix &lt;=V4V0ainfix &lt;=aminmaxV2V3V0ainfix =V4aminmaxV2V3ainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Laposition_valueV2Iainfix =V3c0Iainfix &gt;=V3c0F">
......@@ -352,7 +352,7 @@
locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15"
expl="1. postcondition"
sum="14bc192e3ae00bd1a7b80a8504aae3b8"
sum="4164e1b94ff1bbc17d88e19ea42fcf4d"
proved="true"
expanded="false"
shape="postconditionainfix =V4aminmaxV2V3Iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Laposition_valueV2Iainfix =V3c0Iainfix &gt;=V3c0F">
......@@ -380,7 +380,7 @@
locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15"
expl="2. postcondition"
sum="3b1aac0f9ace3282f582b103139f7704"
sum="52040ad70852ccae8488ca23c44a88ad"
proved="true"
expanded="false"
shape="postconditionainfix &lt;=V4V0Iainfix &lt;=aminmaxV2V3V0INainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Laposition_valueV2Iainfix =V3c0Iainfix &gt;=V3c0F">
......@@ -408,7 +408,7 @@
locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15"
expl="3. postcondition"
sum="189a5206133eba38afac02b6253dcb74"
sum="b3ae9d41235093b43f0fc1f072faa244"
proved="true"
expanded="false"
shape="postconditionainfix &gt;=V4V1INainfix &lt;=aminmaxV2V3V0INainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Laposition_valueV2Iainfix =V3c0Iainfix &gt;=V3c0F">
......@@ -438,7 +438,7 @@
locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15"
expl="2. postcondition"
sum="afcde116ca7f2ded744a62399c9c6e90"
sum="65c667a48f56bcf053cd006a34e8c503"
proved="true"
expanded="false"
shape="postconditionCiiainfix &gt;=V4V1ainfix &lt;=V4V0ainfix &lt;=aminmaxV2V3V0ainfix =V4aminmaxV2V3ainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Laposition_valueV2aNiltaConsVValegal_movesV2INainfix =V3c0Iainfix &gt;=V3c0F">
......@@ -453,7 +453,7 @@
locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15"
expl="1. postcondition"
sum="d7df61293877c9ac68b2a58e3827c0a5"
sum="c2100c185ec5bd38d60c9b6a2fd669bc"
proved="true"
expanded="false"
shape="postconditionCainfix =V4aminmaxV2V3Iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Laposition_valueV2aNiltaConsVValegal_movesV2INainfix =V3c0Iainfix &gt;=V3c0F">
......@@ -489,7 +489,7 @@
locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15"
expl="2. postcondition"
sum="28a84ccab05e78a87ee3baf28a3014b4"
sum="75c132846ee7fc22be4b7c8e8ce2929e"
proved="true"
expanded="false"
shape="postconditionCainfix &lt;=V4V0Iainfix &lt;=aminmaxV2V3V0INainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Laposition_valueV2aNiltaConsVValegal_movesV2INainfix =V3c0Iainfix &gt;=V3c0F">
......@@ -525,7 +525,7 @@
locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15"
expl="3. postcondition"
sum="4b839296c81afd6587c0aaa462c0863f"
sum="f622ea7fc0c52c83e165c80090ef4904"
proved="true"
expanded="false"
shape="postconditionCainfix &gt;=V4V1INainfix &lt;=aminmaxV2V3V0INainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Laposition_valueV2aNiltaConsVValegal_movesV2INainfix =V3c0Iainfix &gt;=V3c0F">
......@@ -563,7 +563,7 @@
locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15"
expl="3. precondition"
sum="82bb910e4ca5d7c49ca3b6e1d7be88ac"
sum="aef005466f060aa69b73388674f7f361"
proved="true"
expanded="false"
shape="preconditionCtaNilainfix &gt;=V3c1aConsVValegal_movesV2INainfix =V3c0Iainfix &gt;=V3c0F">
......@@ -599,7 +599,7 @@
locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15"
expl="4. postcondition"
sum="0a2fe6dbcd49dd5e1a0df01bb03f650b"
sum="0dacec09eefcc86eff23a45f9da0ead4"
proved="false"
expanded="true"
shape="postconditionCtaNiliiainfix &gt;=V6V1ainfix &lt;=V6V0ainfix &lt;=aminmaxV2V3V0ainfix =V6aminmaxV2V3ainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Iainfix &gt;=V6V1Iiiainfix &lt;=V6V0ainfix &gt;=V6V1ainfix &lt;=V7aprefix -V1ainfix =V6aprefix -V7ainfix &lt;V7aprefix -V0Aainfix &lt;aprefix -V1V7Laminmaxado_moveV2V4ainfix -V3c1FIainfix &gt;=V3c1aConsVValegal_movesV2INainfix =V3c0Iainfix &gt;=V3c0F">
......@@ -611,7 +611,7 @@
locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15"
expl="5. precondition"
sum="4d27c1bd77495733b7888ab6f4476fd9"
sum="2ff311f4242e2dd3d5c9641754c8c8e0"
proved="true"
expanded="false"
shape="preconditionCtaNilainfix &gt;=V3c1LamaxV6V0INainfix &gt;=V6V1Iiiainfix &lt;=V6V0ainfix &gt;=V6V1ainfix &lt;=V8aprefix -V1ainfix =V6aprefix -V8ainfix &lt;V8aprefix -V0Aainfix &lt;aprefix -V1V8Laminmaxado_moveV2V4ainfix -V3c1FIainfix &gt;=V3c1aConsVValegal_movesV2INainfix =V3c0Iainfix &gt;=V3c0F">
......@@ -647,7 +647,7 @@
locfile="../alphaBeta.mlw"
loclnum="121" loccnumb="7" loccnume="15"
expl="6. postcondition"
sum="4e1a92fdd2ad92a85a7ee66ae9e72668"
sum="9f5b4f07c5a0e7ab8ad80b406e8ca739"
proved="false"
expanded="true"
shape="postconditionCtaNiliiainfix &gt;=V8V1ainfix &lt;=V8V0ainfix &lt;=aminmaxV2V3V0ainfix =V8aminmaxV2V3ainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Iiiiainfix &gt;=V8V1ainfix &lt;=V8V7ainfix &lt;=V10V7ainfix =V8V10ainfix &lt;V10V1Aainfix &lt;V7V10LaminaTuple2V2V3V9ainfix =V8V6ais_emptyV9LaelementsV5FIainfix &gt;=V3c1LamaxV6V0INainfix &gt;=V6V1Iiiainfix &lt;=V6V0ainfix &gt;=V6V1ainfix &lt;=V11aprefix -V1ainfix =V6aprefix -V11ainfix &lt;V11aprefix -V0Aainfix &lt;aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1FIainfix &gt;=V3c1aConsVValegal_movesV2INainfix =V3c0Iainfix &gt;=V3c0F">
......@@ -661,7 +661,7 @@
locfile="../alphaBeta.mlw"
loclnum="139" loccnumb="7" loccnume="19"
expl="VC for negabeta_rec"
sum="d23f7bac344975e58ad81015254f9623"
sum="26c0dd6c3becae34d82fcf58ed5f776c"
proved="false"
expanded="true"
shape="Ciiainfix &gt;=V4V1ainfix &lt;=V4V0ainfix &lt;=V7V0ainfix =V4V7ainfix &lt;V7V1Aainfix &lt;V0V7LaminaTuple2V2V3V6INais_emptyV6LaelementsV5aNiliiiiainfix &gt;=V13V1ainfix &lt;=V13V0ainfix &lt;=V15V0ainfix =V13V15ainfix &lt;V15V1Aainfix &lt;V0V15LaminaTuple2V2V3V14ainfix =V13V4ais_emptyV14LaelementsV5Iiiiainfix &gt;=V13V1ainfix &lt;=V13V12ainfix &lt;=V17V12ainfix =V13V17ainfix &lt;V17V1Aainfix &lt;V12V17LaminaTuple2V2V3V16ainfix =V13V11ais_emptyV16LaelementsV9FAainfix &gt;=V3c1LamaxV11V0iiiainfix &gt;=V11V1ainfix &lt;=V11V0ainfix &lt;=V19V0ainfix =V11V19ainfix &lt;V19V1Aainfix &lt;V0V19LaminaTuple2V2V3V18ainfix =V11V4ais_emptyV18LaelementsV5ainfix &gt;=V11V1LamaxV10V4Iiiainfix &lt;=V10V0ainfix &gt;=V10V1ainfix &lt;=V20aprefix -V1ainfix =V10aprefix -V20ainfix &lt;V20aprefix -V0Aainfix &lt;aprefix -V1V20Laminmaxado_moveV2V8ainfix -V3c1FAainfix &gt;=V3c1aConsVVV5Iainfix &gt;=V3c1F">
......@@ -676,7 +676,7 @@
locfile="../alphaBeta.mlw"
loclnum="139" loccnumb="7" loccnume="19"
expl="1. postcondition"
sum="73aef1472406a280999a4fdbdd583468"
sum="e7d8dd92a3819de87e861df63c05371a"
proved="true"
expanded="false"
shape="postconditionCiiainfix &gt;=V4V1ainfix &lt;=V4V0ainfix &lt;=V7V0ainfix =V4V7ainfix &lt;V7V1Aainfix &lt;V0V7LaminaTuple2V2V3V6INais_emptyV6LaelementsV5aNiltaConsVVV5Iainfix &gt;=V3c1F">
......@@ -696,7 +696,7 @@
locfile="../alphaBeta.mlw"
loclnum="139" loccnumb="7" loccnume="19"
expl="2. precondition"
sum="3ea1cf951a295a0438db8d797506dfae"
sum="8dfefa9409b3503d0b945636d6618466"
proved="true"
expanded="false"
shape="preconditionCtaNilainfix &gt;=V3c1aConsVVV5Iainfix &gt;=V3c1F">
......@@ -716,7 +716,7 @@
locfile="../alphaBeta.mlw"
loclnum="139" loccnumb="7" loccnume="19"
expl="3. postcondition"
sum="11f1f1c790e92f93845ac9609f82ec97"
sum="4efc4908328f6898158cbd0c734708e8"
proved="false"
expanded="true"
shape="postconditionCtaNiliiiainfix &gt;=V9V1ainfix &lt;=V9V0ainfix &lt;=V11V0ainfix =V9V11ainfix &lt;V11V1Aainfix &lt;V0V11LaminaTuple2V2V3V10ainfix =V9V4ais_emptyV10LaelementsV5Iainfix &gt;=V9V1LamaxV8V4Iiiainfix &lt;=V8V0ainfix &gt;=V8V1ainfix &lt;=V12aprefix -V1ainfix =V8aprefix -V12ainfix &lt;V12aprefix -V0Aainfix &lt;aprefix -V1V12Laminmaxado_moveV2V6ainfix -V3c1FIainfix &gt;=V3c1aConsVVV5Iainfix &gt;=V3c1F">
......@@ -728,7 +728,7 @@
locfile="../alphaBeta.mlw"
loclnum="139" loccnumb="7" loccnume="19"
expl="4. precondition"
sum="9717d46d1a16d84331eac896ba258304"
sum="38e6e2bfb1000ba8db7a62873a22345a"
proved="true"
expanded="false"
shape="preconditionCtaNilainfix &gt;=V3c1LamaxV9V0INainfix &gt;=V9V1LamaxV8V4Iiiainfix &lt;=V8V0ainfix &gt;=V8V1ainfix &lt;=V11aprefix -V1ainfix =V8aprefix -V11ainfix &lt;V11aprefix -V0Aainfix &lt;aprefix -V1V11Laminmaxado_moveV2V6ainfix -V3c1FIainfix &gt;=V3c1aConsVVV5Iainfix &gt;=V3c1F">
......@@ -748,7 +748,7 @@
locfile="../alphaBeta.mlw"
loclnum="139" loccnumb="7" loccnume="19"
expl="5. postcondition"
sum="fd91d12fec269921cad9b0a022668e3b"
sum="89398fbaa9f239a49670bc10089323a6"
proved="false"
expanded="true"
shape="postconditionCtaNiliiiainfix &gt;=V11V1ainfix &lt;=V11V0ainfix &lt;=V13V0ainfix =V11V13ainfix &lt;V13V1Aainfix &lt;V0V13LaminaTuple2V2V3V12ainfix =V11V4ais_emptyV12LaelementsV5Iiiiainfix &gt;=V11V1ainfix &lt;=V11V10ainfix &lt;=V15V10ainfix =V11V15ainfix &lt;V15V1Aainfix &lt;V10V15LaminaTuple2V2V3V14ainfix =V11V9ais_emptyV14LaelementsV7FIainfix &gt;=V3c1LamaxV9V0INainfix &gt;=V9V1LamaxV8V4Iiiainfix &lt;=V8V0ainfix &gt;=V8V1ainfix &lt;=V16aprefix -V1ainfix =V8aprefix -V16ainfix &lt;V16aprefix -V0Aainfix &lt;aprefix -V1V16Laminmaxado_moveV2V6ainfix -V3c1FIainfix &gt;=V3c1aConsVVV5Iainfix &gt;=V3c1F">
......@@ -762,7 +762,7 @@
locfile="../alphaBeta.mlw"
loclnum="161" loccnumb="4" loccnume="14"
expl="VC for alpha_beta"
sum="74aa737887ec0d637f394aee463c1610"
sum="58d1fe56c4bb9e80dd6a94c960150e0f"
proved="true"
expanded="false"
shape="ainfix =V4aminmaxV0V1Iiiainfix &gt;=V4V2ainfix &lt;=V4V3ainfix &lt;=aminmaxV0V1V3ainfix =V4aminmaxV0V1ainfix &lt;aminmaxV0V1V2Aainfix &lt;V3aminmaxV0V1FAainfix &gt;=V1c0Laprefix -ainfinityLainfinityIainfix &gt;=V1c0F">
......
......@@ -24,7 +24,7 @@
locfile="../arm.mlw"
loclnum="16" loccnumb="6" loccnume="20"
expl="VC for insertion_sort"
sum="5677a170e9f6faf600b34c4281eebd63"
sum="ff4534d299565274c09d1a7200c24c10"
proved="false"
expanded="false"
shape="iainfix &lt;=V6c45Aainfix =V7c9Aainfix &lt;=c0V0iainfix &lt;ainfix -c10V16ainfix -c10V5Aainfix &lt;=c0ainfix -c10V5Aainfix &lt;=ainfix *c2V12ainfix *ainfix -V16c2ainfix -V16c1Aainfix =V10ainfix -V16c2AainvV14Aainfix &lt;=V16c11Aainfix &lt;=c2V16Iainfix =V16ainfix +V5c1Fainfix &lt;V22V11Aainfix &lt;=c0V11Aainfix &lt;=ainfix *c2V17ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V22Aainvamk arrayV0V21Aainfix &lt;=V22V5Aainfix &lt;=c1V22Iainfix =V22ainfix -V11c1FIainfix =V21asetV19V20agetV13V11Aainfix &lt;=c0V0FAainfix &lt;V20V0Aainfix &lt;=c0V20Lainfix -V11c1Iainfix =V19asetV13V11agetV13V18Aainfix &lt;=c0V0FAainfix &lt;V11V0Aainfix &lt;=c0V11Aainfix &lt;V18V0Aainfix &lt;=c0V18Lainfix -V11c1Aainfix &lt;V11V0Aainfix &lt;=c0V11Iainfix =V17ainfix +V12c1Fainfix &lt;agetV13V11agetV13V15Aainfix &lt;V11V0Aainfix &lt;=c0V11Aainfix &lt;V15V0Aainfix &lt;=c0V15Aainfix &lt;=c0V0Lainfix -V11c1Iainfix &lt;=ainfix *c2V12ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V11AainvV14Aainfix &lt;=V11V5Aainfix &lt;=c1V11Lamk arrayV0V13FAainfix &lt;=ainfix *c2V6ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V5AainvV9Aainfix &lt;=V5V5Aainfix &lt;=c1V5Iainfix =V10ainfix +V7c1Fainfix &lt;=V5c10Iainfix &lt;=ainfix *c2V6ainfix *ainfix -V5c2ainfix -V5c1Aainfix =V7ainfix -V5c2AainvV9Aainfix &lt;=V5c11Aainfix &lt;=c2V5Lamk arrayV0V8FAainfix &lt;=ainfix *c2V1ainfix *ainfix -c2c2ainfix -c2c1Aainfix =V2ainfix -c2c2AainvV4Aainfix &lt;=c2c11Aainfix &lt;=c2c2Iainfix =V1c0Aainfix =V2c0AainvV4Aainfix &lt;=c0V0Lamk arrayV0V3FF">
......@@ -50,7 +50,7 @@
locfile="../arm.mlw"
loclnum="120" loccnumb="6" loccnume="18"
expl="VC for path_init_l2"
sum="19ae2913cea5458fb6929fc9f238efaf"
sum="a673c6b14e3f66097ab6521a75fc2975"
proved="true"
expanded="true"
shape="ainv_l2V5V0V2Iainfix =V5amixfix [&lt;-]V1ainfix -V0c16V4FIainfix =V4c2FIainfix =V3c0FIainfix =V2c0FIainvV1AaseparationV0F">
......@@ -70,7 +70,7 @@
memlimit="1000"
obsolete="false"