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Why3
why3
Commits
9874f16a
Commit
9874f16a
authored
Mar 16, 2012
by
MARCHE Claude
Browse files
add function
parent
67ffdc8a
Changes
1
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examples/hoare_logic/wp2.mlw
View file @
9874f16a
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@@ -384,6 +384,15 @@ module WP
ident
{ fresh_in_fmla result q }
val abstract_effects (i:stmt) (f:fmla) :
{ }
fmla
{ forall sigma pi sigma' pi':env .
eval_fmla sigma pi f /\
assigns sigma pi (stmt_writes i) sigma' pi' ->
eval_fmla sigma' pi' f
}
let rec wp (i:stmt) (q:fmla) =
{ true }
match i with
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@@ -399,9 +408,10 @@ module WP
(* Fand f q *) (* strict wp, termination required *)
| Swhile e inv i ->
Fand inv
((*Fforall*) (Fand
(Fimplies (Fand (Fterm e) inv) (wp i inv))
(Fimplies (Fand (Fnot (Fterm e)) inv) q)))
(abstract_effects i
(Fand
(Fimplies (Fand (Fterm e) inv) (wp i inv))
(Fimplies (Fand (Fnot (Fterm e)) inv) q)))
end
{ valid_triple result i q }
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