repair sessions

examples/add_list/why3session.xml

@@ -71,10 +71,10 @@
     locfile="../add_list.mlw"
     loclnum="44" loccnumb="4" loccnume="8"
     expl="VC for main"
-    sum="1e59a24fb282a191a17e4debdff0ca6e"
+    sum="3addecdc3def08b9d84f78ae1b651633"
     proved="true"
     expanded="true"
-    shape="ainfix =V1c4.7Aainfix =V0c22Iainfix =V1aadd_realaConsaIntegerc5aConsaRealc3.3aConsaIntegerc8aConsaRealc1.4aConsaIntegerc9aNilAainfix =V0aadd_intaConsaIntegerc5aConsaRealc3.3aConsaIntegerc8aConsaRealc1.4aConsaIntegerc9aNilF">
+    shape="ainfix =V2c4.7Aainfix =V1c22Iainfix =V2aadd_realV0Aainfix =V1aadd_intV0FLaConsaIntegerc5aConsaRealc3.3aConsaIntegerc8aConsaRealc1.4aConsaIntegerc9aNil">
     <label
      name="expl:VC for main"/>
     <proof
@@ -134,10 +134,10 @@
     locfile="../add_list.mlw"
     loclnum="86" loccnumb="4" loccnume="8"
     expl="VC for main"
-    sum="9a71ed6f77f4b28ff9d67782ed191026"
+    sum="14865656d7430b23243e556d7d49e6c7"
     proved="true"
     expanded="true"
-    shape="ainfix =V1c4.7Aainfix =V0c22Iainfix =V1aadd_realaConsaIntegerc5aConsaRealc3.3aConsaIntegerc8aConsaRealc1.4aConsaIntegerc9aNilAainfix =V0aadd_intaConsaIntegerc5aConsaRealc3.3aConsaIntegerc8aConsaRealc1.4aConsaIntegerc9aNilF">
+    shape="ainfix =V2c4.7Aainfix =V1c22Iainfix =V2aadd_realV0Aainfix =V1aadd_intV0FLaConsaIntegerc5aConsaRealc3.3aConsaIntegerc8aConsaRealc1.4aConsaIntegerc9aNil">
     <label
      name="expl:VC for main"/>
     <proof

examples/alphaBeta/why3session.xml

@@ -160,10 +160,10 @@
     locfile="../alphaBeta.mlw"
     loclnum="109" loccnumb="10" loccnume="31"
     expl="VC for move_value_alpha_beta"
-    sum="a332a9c8f7688c122f1579e6af887e53"
+    sum="5974256969be47144ed719ff72f9bff3"
     proved="true"
     expanded="false"
-    shape="iainfix <V6aprefix -V0Aainfix <aprefix -V1V6ainfix =aprefix -V5aprefix -V6iainfix <=V6aprefix -V1ainfix >=aprefix -V5V1ainfix <=aprefix -V5V0Laminmaxado_moveV2V4ainfix -V3c1Iiainfix <aminmaxado_moveV2V4ainfix -V3c1aprefix -V0Aainfix <aprefix -V1aminmaxado_moveV2V4ainfix -V3c1ainfix =V5aminmaxado_moveV2V4ainfix -V3c1iainfix <=aminmaxado_moveV2V4ainfix -V3c1aprefix -V1ainfix <=V5aprefix -V1ainfix >=V5aprefix -V0FAainfix >=ainfix -V3c1c0Iainfix >=V3c1F">
+    shape="iainfix <V11aprefix -V0Aainfix <aprefix -V1V11ainfix =V10aprefix -V11iainfix <=V11aprefix -V1ainfix >=V10V1ainfix <=V10V0Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiainfix <aminmaxV5V6V7Aainfix <V8aminmaxV5V6ainfix =V9aminmaxV5V6iainfix <=aminmaxV5V6V8ainfix <=V9V8ainfix >=V9V7FAainfix >=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix >=V3c1F">
     <label
      name="expl:VC for move_value_alpha_beta"/>
     <transf
@@ -175,10 +175,10 @@
       locfile="../alphaBeta.mlw"
       loclnum="109" loccnumb="10" loccnume="31"
       expl="1. precondition"
-      sum="06278163163a9df94de2a2cc153cea8f"
+      sum="4f8f54ce3efd51c86432f42c423a8eb0"
       proved="true"
       expanded="false"
-      shape="ainfix &gt;=ainfix -V3c1c0Iainfix &gt;=V3c1F">
+      shape="ainfix &gt;=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix &gt;=V3c1F">
       <label
        name="expl:VC for move_value_alpha_beta"/>
       <proof
@@ -235,10 +235,10 @@
       locfile="../alphaBeta.mlw"
       loclnum="109" loccnumb="10" loccnume="31"
       expl="2. postcondition"
-      sum="ac507ff1b6f5460ac814583862d1895c"
+      sum="b9473518c9c500752845999b7f470c14"
       proved="true"
       expanded="false"
-      shape="iainfix &lt;V6aprefix -V0Aainfix &lt;aprefix -V1V6ainfix =aprefix -V5aprefix -V6iainfix &lt;=V6aprefix -V1ainfix &gt;=aprefix -V5V1ainfix &lt;=aprefix -V5V0Laminmaxado_moveV2V4ainfix -V3c1Iiainfix &lt;aminmaxado_moveV2V4ainfix -V3c1aprefix -V0Aainfix &lt;aprefix -V1aminmaxado_moveV2V4ainfix -V3c1ainfix =V5aminmaxado_moveV2V4ainfix -V3c1iainfix &lt;=aminmaxado_moveV2V4ainfix -V3c1aprefix -V1ainfix &lt;=V5aprefix -V1ainfix &gt;=V5aprefix -V0FIainfix &gt;=ainfix -V3c1c0Iainfix &gt;=V3c1F">
+      shape="iainfix &lt;V11aprefix -V0Aainfix &lt;aprefix -V1V11ainfix =V10aprefix -V11iainfix &lt;=V11aprefix -V1ainfix &gt;=V10V1ainfix &lt;=V10V0Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiainfix &lt;aminmaxV5V6V7Aainfix &lt;V8aminmaxV5V6ainfix =V9aminmaxV5V6iainfix &lt;=aminmaxV5V6V8ainfix &lt;=V9V8ainfix &gt;=V9V7FIainfix &gt;=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix &gt;=V3c1F">
       <label
        name="expl:VC for move_value_alpha_beta"/>
       <transf
@@ -250,10 +250,10 @@
         locfile="../alphaBeta.mlw"
         loclnum="109" loccnumb="10" loccnume="31"
         expl="1. postcondition"
-        sum="c12f95a92138357c66b05d621b418cba"
+        sum="e85ec6b2c57edf43b4a62891b2cbd726"
         proved="true"
         expanded="false"
-        shape="ainfix =aprefix -V5aprefix -V6Iainfix &lt;V6aprefix -V0Aainfix &lt;aprefix -V1V6Laminmaxado_moveV2V4ainfix -V3c1Iiainfix &lt;aminmaxado_moveV2V4ainfix -V3c1aprefix -V0Aainfix &lt;aprefix -V1aminmaxado_moveV2V4ainfix -V3c1ainfix =V5aminmaxado_moveV2V4ainfix -V3c1iainfix &lt;=aminmaxado_moveV2V4ainfix -V3c1aprefix -V1ainfix &lt;=V5aprefix -V1ainfix &gt;=V5aprefix -V0FIainfix &gt;=ainfix -V3c1c0Iainfix &gt;=V3c1F">
+        shape="ainfix =V10aprefix -V11Iainfix &lt;V11aprefix -V0Aainfix &lt;aprefix -V1V11Laminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiainfix &lt;aminmaxV5V6V7Aainfix &lt;V8aminmaxV5V6ainfix =V9aminmaxV5V6iainfix &lt;=aminmaxV5V6V8ainfix &lt;=V9V8ainfix &gt;=V9V7FIainfix &gt;=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix &gt;=V3c1F">
         <label
          name="expl:VC for move_value_alpha_beta"/>
         <proof
@@ -270,10 +270,10 @@
         locfile="../alphaBeta.mlw"
         loclnum="109" loccnumb="10" loccnume="31"
         expl="2. postcondition"
-        sum="f346ce905ab570c3e6acee9c1d75b860"
+        sum="1a57d9cf91cccc0d13cc730e1818524b"
         proved="true"
         expanded="false"
-        shape="ainfix &gt;=aprefix -V5V1Iainfix &lt;=V6aprefix -V1Iainfix &lt;V6aprefix -V0Aainfix &lt;aprefix -V1V6NLaminmaxado_moveV2V4ainfix -V3c1Iiainfix &lt;aminmaxado_moveV2V4ainfix -V3c1aprefix -V0Aainfix &lt;aprefix -V1aminmaxado_moveV2V4ainfix -V3c1ainfix =V5aminmaxado_moveV2V4ainfix -V3c1iainfix &lt;=aminmaxado_moveV2V4ainfix -V3c1aprefix -V1ainfix &lt;=V5aprefix -V1ainfix &gt;=V5aprefix -V0FIainfix &gt;=ainfix -V3c1c0Iainfix &gt;=V3c1F">
+        shape="ainfix &gt;=V10V1Iainfix &lt;=V11aprefix -V1Iainfix &lt;V11aprefix -V0Aainfix &lt;aprefix -V1V11NLaminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiainfix &lt;aminmaxV5V6V7Aainfix &lt;V8aminmaxV5V6ainfix =V9aminmaxV5V6iainfix &lt;=aminmaxV5V6V8ainfix &lt;=V9V8ainfix &gt;=V9V7FIainfix &gt;=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix &gt;=V3c1F">
         <label
          name="expl:VC for move_value_alpha_beta"/>
         <proof
@@ -290,10 +290,10 @@
         locfile="../alphaBeta.mlw"
         loclnum="109" loccnumb="10" loccnume="31"
         expl="3. postcondition"
-        sum="bbf93aeaaf1d14daed633dae2ea77649"
+        sum="77612ad6c2e8b1b8e726358fff18f6c1"
         proved="true"
         expanded="false"
-        shape="ainfix &lt;=aprefix -V5V0Iainfix &lt;=V6aprefix -V1NIainfix &lt;V6aprefix -V0Aainfix &lt;aprefix -V1V6NLaminmaxado_moveV2V4ainfix -V3c1Iiainfix &lt;aminmaxado_moveV2V4ainfix -V3c1aprefix -V0Aainfix &lt;aprefix -V1aminmaxado_moveV2V4ainfix -V3c1ainfix =V5aminmaxado_moveV2V4ainfix -V3c1iainfix &lt;=aminmaxado_moveV2V4ainfix -V3c1aprefix -V1ainfix &lt;=V5aprefix -V1ainfix &gt;=V5aprefix -V0FIainfix &gt;=ainfix -V3c1c0Iainfix &gt;=V3c1F">
+        shape="ainfix &lt;=V10V0Iainfix &lt;=V11aprefix -V1NIainfix &lt;V11aprefix -V0Aainfix &lt;aprefix -V1V11NLaminmaxado_moveV2V4ainfix -V3c1Laprefix -V9Iiainfix &lt;aminmaxV5V6V7Aainfix &lt;V8aminmaxV5V6ainfix =V9aminmaxV5V6iainfix &lt;=aminmaxV5V6V8ainfix &lt;=V9V8ainfix &gt;=V9V7FIainfix &gt;=V6c0Laprefix -V1Laprefix -V0Lainfix -V3c1Lado_moveV2V4Iainfix &gt;=V3c1F">
         <label
          name="expl:VC for move_value_alpha_beta"/>
         <proof
@@ -314,10 +314,10 @@
     locfile="../alphaBeta.mlw"
     loclnum="121" loccnumb="7" loccnume="15"
     expl="VC for negabeta"
-    sum="29ce0e7f8822b15d21ad679421c83ee9"
+    sum="4c3e8b26475ef944744a3429afb84c4a"
     proved="false"
     expanded="true"
-    shape="iainfix =V3c0iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix =aposition_valueV2aminmaxV2V3iainfix &lt;=aminmaxV2V3V0ainfix &lt;=aposition_valueV2V0ainfix &gt;=aposition_valueV2V1Calegal_movesV2aNiliainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix =aposition_valueV2aminmaxV2V3iainfix &lt;=aminmaxV2V3V0ainfix &lt;=aposition_valueV2V0ainfix &gt;=aposition_valueV2V1aConsVViainfix &gt;=V6V1iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix =V6aminmaxV2V3iainfix &lt;=aminmaxV2V3V0ainfix &lt;=V6V0ainfix &gt;=V6V1iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix =V7aminmaxV2V3iainfix &lt;=aminmaxV2V3V0ainfix &lt;=V7V0ainfix &gt;=V7V1Iiais_emptyV8ainfix =V7V6iainfix &lt;V9V1Aainfix &lt;amaxV6V0V9ainfix =V7V9iainfix &lt;=V9amaxV6V0ainfix &lt;=V7amaxV6V0ainfix &gt;=V7V1LaminaTuple2V2V3V8LaelementsV5FAainfix &gt;=V3c1Iiainfix &lt;V10aprefix -V0Aainfix &lt;aprefix -V1V10ainfix =V6aprefix -V10iainfix &lt;=V10aprefix -V1ainfix &gt;=V6V1ainfix &lt;=V6V0Laminmaxado_moveV2V4ainfix -V3c1FAainfix &gt;=V3c1Iainfix &gt;=V3c0F">
+    shape="iainfix =V3c0iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix =V4aminmaxV2V3iainfix &lt;=aminmaxV2V3V0ainfix &lt;=V4V0ainfix &gt;=V4V1Laposition_valueV2Calegal_movesV2aNiliainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix =V5aminmaxV2V3iainfix &lt;=aminmaxV2V3V0ainfix &lt;=V5V0ainfix &gt;=V5V1Laposition_valueV2aConsVViainfix &gt;=V8V1iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix =V8aminmaxV2V3iainfix &lt;=aminmaxV2V3V0ainfix &lt;=V8V0ainfix &gt;=V8V1iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix =V10aminmaxV2V3iainfix &lt;=aminmaxV2V3V0ainfix &lt;=V10V0ainfix &gt;=V10V1Iiais_emptyV11ainfix =V10V8iainfix &lt;V12V1Aainfix &lt;V9V12ainfix =V10V12iainfix &lt;=V12V9ainfix &lt;=V10V9ainfix &gt;=V10V1LaminaTuple2V2V3V11LaelementsV7FAainfix &gt;=V3c1LamaxV8V0Iiainfix &lt;V13aprefix -V0Aainfix &lt;aprefix -V1V13ainfix =V8aprefix -V13iainfix &lt;=V13aprefix -V1ainfix &gt;=V8V1ainfix &lt;=V8V0Laminmaxado_moveV2V6ainfix -V3c1FAainfix &gt;=V3c1Iainfix &gt;=V3c0F">
     <label
      name="expl:VC for negabeta"/>
     <transf
@@ -329,10 +329,10 @@
       locfile="../alphaBeta.mlw"
       loclnum="121" loccnumb="7" loccnume="15"
       expl="1. postcondition"
-      sum="17436e5ad6f404a6d6b118a3dd501a78"
+      sum="3ac6052ce9786e59d863ad8f8e47f0a0"
       proved="true"
       expanded="false"
-      shape="iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix =aposition_valueV2aminmaxV2V3iainfix &lt;=aminmaxV2V3V0ainfix &lt;=aposition_valueV2V0ainfix &gt;=aposition_valueV2V1Iainfix =V3c0Iainfix &gt;=V3c0F">
+      shape="iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix =V4aminmaxV2V3iainfix &lt;=aminmaxV2V3V0ainfix &lt;=V4V0ainfix &gt;=V4V1Laposition_valueV2Iainfix =V3c0Iainfix &gt;=V3c0F">
       <label
        name="expl:VC for negabeta"/>
       <proof
@@ -352,10 +352,10 @@
         locfile="../alphaBeta.mlw"
         loclnum="121" loccnumb="7" loccnume="15"
         expl="1. postcondition"
-        sum="977619128dc2ac90b9ee2dbb22d1dda1"
+        sum="81633d72c54aa3f2a70c5477a0d869f3"
         proved="true"
         expanded="false"
-        shape="ainfix =aposition_valueV2aminmaxV2V3Iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Iainfix =V3c0Iainfix &gt;=V3c0F">
+        shape="ainfix =V4aminmaxV2V3Iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Laposition_valueV2Iainfix =V3c0Iainfix &gt;=V3c0F">
         <label
          name="expl:VC for negabeta"/>
         <proof
@@ -380,10 +380,10 @@
         locfile="../alphaBeta.mlw"
         loclnum="121" loccnumb="7" loccnume="15"
         expl="2. postcondition"
-        sum="eb9265336a8e61bc709fe742b4767cc8"
+        sum="d33e8a8377b22c94a18ffae66af3c9e6"
         proved="true"
         expanded="false"
-        shape="ainfix &lt;=aposition_valueV2V0Iainfix &lt;=aminmaxV2V3V0Iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3NIainfix =V3c0Iainfix &gt;=V3c0F">
+        shape="ainfix &lt;=V4V0Iainfix &lt;=aminmaxV2V3V0Iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3NLaposition_valueV2Iainfix =V3c0Iainfix &gt;=V3c0F">
         <label
          name="expl:VC for negabeta"/>
         <proof
@@ -408,10 +408,10 @@
         locfile="../alphaBeta.mlw"
         loclnum="121" loccnumb="7" loccnume="15"
         expl="3. postcondition"
-        sum="dafb041d825b78bfab27ba7b89696a15"
+        sum="52ccf7cdcfca2a72549cc274d96be645"
         proved="true"
         expanded="false"
-        shape="ainfix &gt;=aposition_valueV2V1Iainfix &lt;=aminmaxV2V3V0NIainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3NIainfix =V3c0Iainfix &gt;=V3c0F">
+        shape="ainfix &gt;=V4V1Iainfix &lt;=aminmaxV2V3V0NIainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3NLaposition_valueV2Iainfix =V3c0Iainfix &gt;=V3c0F">
         <label
          name="expl:VC for negabeta"/>
         <proof
@@ -438,10 +438,10 @@
       locfile="../alphaBeta.mlw"
       loclnum="121" loccnumb="7" loccnume="15"
       expl="2. postcondition"
-      sum="179e6b3c84c4f07b9e5f4b6de2fa8730"
+      sum="1067614cb081235803394fa759e2b264"
       proved="true"
       expanded="false"
-      shape="Calegal_movesV2aNiliainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix =aposition_valueV2aminmaxV2V3iainfix &lt;=aminmaxV2V3V0ainfix &lt;=aposition_valueV2V0ainfix &gt;=aposition_valueV2V1aConsVVtIainfix =V3c0NIainfix &gt;=V3c0F">
+      shape="Calegal_movesV2aNiliainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix =V4aminmaxV2V3iainfix &lt;=aminmaxV2V3V0ainfix &lt;=V4V0ainfix &gt;=V4V1Laposition_valueV2aConsVVtIainfix =V3c0NIainfix &gt;=V3c0F">
       <label
        name="expl:VC for negabeta"/>
       <transf
@@ -453,10 +453,10 @@
         locfile="../alphaBeta.mlw"
         loclnum="121" loccnumb="7" loccnume="15"
         expl="1. postcondition"
-        sum="3762df68709b7a5c5fd90fb64c9448b4"
+        sum="0545d7a0ad5ab4f11760327a225ddf59"
         proved="true"
         expanded="false"
-        shape="Calegal_movesV2aNilainfix =aposition_valueV2aminmaxV2V3Iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3aConsVVtIainfix =V3c0NIainfix &gt;=V3c0F">
+        shape="Calegal_movesV2aNilainfix =V4aminmaxV2V3Iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3Laposition_valueV2aConsVVtIainfix =V3c0NIainfix &gt;=V3c0F">
         <label
          name="expl:VC for negabeta"/>
         <proof
@@ -489,10 +489,10 @@
         locfile="../alphaBeta.mlw"
         loclnum="121" loccnumb="7" loccnume="15"
         expl="2. postcondition"
-        sum="001a47fc69ee51c27e2480ebc843e531"
+        sum="7169cbea929abdbc7d0aac9bc2ba71e1"
         proved="true"
         expanded="false"
-        shape="Calegal_movesV2aNilainfix &lt;=aposition_valueV2V0Iainfix &lt;=aminmaxV2V3V0Iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3NaConsVVtIainfix =V3c0NIainfix &gt;=V3c0F">
+        shape="Calegal_movesV2aNilainfix &lt;=V4V0Iainfix &lt;=aminmaxV2V3V0Iainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3NLaposition_valueV2aConsVVtIainfix =V3c0NIainfix &gt;=V3c0F">
         <label
          name="expl:VC for negabeta"/>
         <proof
@@ -525,10 +525,10 @@
         locfile="../alphaBeta.mlw"
         loclnum="121" loccnumb="7" loccnume="15"
         expl="3. postcondition"
-        sum="352f066a3258e443c30356e719b51441"
+        sum="285aa67078cabb60dfaff2aadac67ae8"
         proved="true"
         expanded="false"
-        shape="Calegal_movesV2aNilainfix &gt;=aposition_valueV2V1Iainfix &lt;=aminmaxV2V3V0NIainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3NaConsVVtIainfix =V3c0NIainfix &gt;=V3c0F">
+        shape="Calegal_movesV2aNilainfix &gt;=V4V1Iainfix &lt;=aminmaxV2V3V0NIainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3NLaposition_valueV2aConsVVtIainfix =V3c0NIainfix &gt;=V3c0F">
         <label
          name="expl:VC for negabeta"/>
         <proof
@@ -611,10 +611,10 @@
       locfile="../alphaBeta.mlw"
       loclnum="121" loccnumb="7" loccnume="15"
       expl="5. precondition"
-      sum="c813873e116daf8c76d9ece64eec19ed"
+      sum="6893fd7b4b212c1c6e2be1271676546e"
       proved="true"
       expanded="false"
-      shape="Calegal_movesV2aNiltaConsVVainfix &gt;=V3c1Iainfix &gt;=V6V1NIiainfix &lt;V7aprefix -V0Aainfix &lt;aprefix -V1V7ainfix =V6aprefix -V7iainfix &lt;=V7aprefix -V1ainfix &gt;=V6V1ainfix &lt;=V6V0Laminmaxado_moveV2V4ainfix -V3c1FIainfix &gt;=V3c1Iainfix =V3c0NIainfix &gt;=V3c0F">
+      shape="Calegal_movesV2aNiltaConsVVainfix &gt;=V3c1LamaxV6V0Iainfix &gt;=V6V1NIiainfix &lt;V8aprefix -V0Aainfix &lt;aprefix -V1V8ainfix =V6aprefix -V8iainfix &lt;=V8aprefix -V1ainfix &gt;=V6V1ainfix &lt;=V6V0Laminmaxado_moveV2V4ainfix -V3c1FIainfix &gt;=V3c1Iainfix =V3c0NIainfix &gt;=V3c0F">
       <label
        name="expl:VC for negabeta"/>
       <proof
@@ -647,10 +647,10 @@
       locfile="../alphaBeta.mlw"
       loclnum="121" loccnumb="7" loccnume="15"
       expl="6. postcondition"
-      sum="a1ccb3c2d0dfa7bc74267f3cd20507cd"
+      sum="6de295bf37be4765e7bf41253ccfeff2"
       proved="false"
       expanded="true"
-      shape="Calegal_movesV2aNiltaConsVViainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix =V7aminmaxV2V3iainfix &lt;=aminmaxV2V3V0ainfix &lt;=V7V0ainfix &gt;=V7V1Iiais_emptyV8ainfix =V7V6iainfix &lt;V9V1Aainfix &lt;amaxV6V0V9ainfix =V7V9iainfix &lt;=V9amaxV6V0ainfix &lt;=V7amaxV6V0ainfix &gt;=V7V1LaminaTuple2V2V3V8LaelementsV5FIainfix &gt;=V3c1Iainfix &gt;=V6V1NIiainfix &lt;V10aprefix -V0Aainfix &lt;aprefix -V1V10ainfix =V6aprefix -V10iainfix &lt;=V10aprefix -V1ainfix &gt;=V6V1ainfix &lt;=V6V0Laminmaxado_moveV2V4ainfix -V3c1FIainfix &gt;=V3c1Iainfix =V3c0NIainfix &gt;=V3c0F">
+      shape="Calegal_movesV2aNiltaConsVViainfix &lt;aminmaxV2V3V1Aainfix &lt;V0aminmaxV2V3ainfix =V8aminmaxV2V3iainfix &lt;=aminmaxV2V3V0ainfix &lt;=V8V0ainfix &gt;=V8V1Iiais_emptyV9ainfix =V8V6iainfix &lt;V10V1Aainfix &lt;V7V10ainfix =V8V10iainfix &lt;=V10V7ainfix &lt;=V8V7ainfix &gt;=V8V1LaminaTuple2V2V3V9LaelementsV5FIainfix &gt;=V3c1LamaxV6V0Iainfix &gt;=V6V1NIiainfix &lt;V11aprefix -V0Aainfix &lt;aprefix -V1V11ainfix =V6aprefix -V11iainfix &lt;=V11aprefix -V1ainfix &gt;=V6V1ainfix &lt;=V6V0Laminmaxado_moveV2V4ainfix -V3c1FIainfix &gt;=V3c1Iainfix =V3c0NIainfix &gt;=V3c0F">
       <label
        name="expl:VC for negabeta"/>
      </goal>
@@ -661,10 +661,10 @@
     locfile="../alphaBeta.mlw"
     loclnum="139" loccnumb="7" loccnume="19"
     expl="VC for negabeta_rec"
-    sum="69e55eb814eca6f45667b8ec7d92451b"
+    sum="1179d627feeacfd1131b60a2ad09f250"
     proved="false"
     expanded="true"
-    shape="CV5aNiliainfix &lt;V7V1Aainfix &lt;V0V7ainfix =V4V7iainfix &lt;=V7V0ainfix &lt;=V4V0ainfix &gt;=V4V1LaminaTuple2V2V3V6Iais_emptyV6NLaelementsV5aConsVViainfix &gt;=amaxV10V4V1iais_emptyV11ainfix =amaxV10V4V4iainfix &lt;V12V1Aainfix &lt;V0V12ainfix =amaxV10V4V12iainfix &lt;=V12V0ainfix &lt;=amaxV10V4V0ainfix &gt;=amaxV10V4V1LaminaTuple2V2V3V11LaelementsV5iais_emptyV14ainfix =V13V4iainfix &lt;V15V1Aainfix &lt;V0V15ainfix =V13V15iainfix &lt;=V15V0ainfix &lt;=V13V0ainfix &gt;=V13V1LaminaTuple2V2V3V14LaelementsV5Iiais_emptyV16ainfix =V13amaxV10V4iainfix &lt;V17V1Aainfix &lt;amaxamaxV10V4V0V17ainfix =V13V17iainfix &lt;=V17amaxamaxV10V4V0ainfix &lt;=V13amaxamaxV10V4V0ainfix &gt;=V13V1LaminaTuple2V2V3V16LaelementsV9FAainfix &gt;=V3c1Iiainfix &lt;V18aprefix -V0Aainfix &lt;aprefix -V1V18ainfix =V10aprefix -V18iainfix &lt;=V18aprefix -V1ainfix &gt;=V10V1ainfix &lt;=V10V0Laminmaxado_moveV2V8ainfix -V3c1FAainfix &gt;=V3c1Iainfix &gt;=V3c1F">
+    shape="CV5aNiliainfix &lt;V7V1Aainfix &lt;V0V7ainfix =V4V7iainfix &lt;=V7V0ainfix &lt;=V4V0ainfix &gt;=V4V1LaminaTuple2V2V3V6Iais_emptyV6NLaelementsV5aConsVViainfix &gt;=V11V1iais_emptyV12ainfix =V11V4iainfix &lt;V13V1Aainfix &lt;V0V13ainfix =V11V13iainfix &lt;=V13V0ainfix &lt;=V11V0ainfix &gt;=V11V1LaminaTuple2V2V3V12LaelementsV5iais_emptyV16ainfix =V15V4iainfix &lt;V17V1Aainfix &lt;V0V17ainfix =V15V17iainfix &lt;=V17V0ainfix &lt;=V15V0ainfix &gt;=V15V1LaminaTuple2V2V3V16LaelementsV5Iiais_emptyV18ainfix =V15V11iainfix &lt;V19V1Aainfix &lt;V14V19ainfix =V15V19iainfix &lt;=V19V14ainfix &lt;=V15V14ainfix &gt;=V15V1LaminaTuple2V2V3V18LaelementsV9FAainfix &gt;=V3c1LamaxV11V0LamaxV10V4Iiainfix &lt;V20aprefix -V0Aainfix &lt;aprefix -V1V20ainfix =V10aprefix -V20iainfix &lt;=V20aprefix -V1ainfix &gt;=V10V1ainfix &lt;=V10V0Laminmaxado_moveV2V8ainfix -V3c1FAainfix &gt;=V3c1Iainfix &gt;=V3c1F">
     <label
      name="expl:VC for negabeta_rec"/>
     <transf
@@ -716,10 +716,10 @@
       locfile="../alphaBeta.mlw"
       loclnum="139" loccnumb="7" loccnume="19"
       expl="3. postcondition"
-      sum="2b94cd9f002f82fa43ff34817ab70272"
+      sum="fab259bd8938f45e5498b4d5669bcc3b"
       proved="false"
       expanded="true"
-      shape="CV5aNiltaConsVViais_emptyV9ainfix =amaxV8V4V4iainfix &lt;V10V1Aainfix &lt;V0V10ainfix =amaxV8V4V10iainfix &lt;=V10V0ainfix &lt;=amaxV8V4V0ainfix &gt;=amaxV8V4V1LaminaTuple2V2V3V9LaelementsV5Iainfix &gt;=amaxV8V4V1Iiainfix &lt;V11aprefix -V0Aainfix &lt;aprefix -V1V11ainfix =V8aprefix -V11iainfix &lt;=V11aprefix -V1ainfix &gt;=V8V1ainfix &lt;=V8V0Laminmaxado_moveV2V6ainfix -V3c1FIainfix &gt;=V3c1Iainfix &gt;=V3c1F">
+      shape="CV5aNiltaConsVViais_emptyV10ainfix =V9V4iainfix &lt;V11V1Aainfix &lt;V0V11ainfix =V9V11iainfix &lt;=V11V0ainfix &lt;=V9V0ainfix &gt;=V9V1LaminaTuple2V2V3V10LaelementsV5Iainfix &gt;=V9V1LamaxV8V4Iiainfix &lt;V12aprefix -V0Aainfix &lt;aprefix -V1V12ainfix =V8aprefix -V12iainfix &lt;=V12aprefix -V1ainfix &gt;=V8V1ainfix &lt;=V8V0Laminmaxado_moveV2V6ainfix -V3c1FIainfix &gt;=V3c1Iainfix &gt;=V3c1F">
       <label
        name="expl:VC for negabeta_rec"/>
      </goal>
@@ -728,10 +728,10 @@
       locfile="../alphaBeta.mlw"
       loclnum="139" loccnumb="7" loccnume="19"
       expl="4. precondition"
-      sum="afc7b06cfeb1c7fb6fe3af31328df1c6"
+      sum="6cfdae56022b041afa87e0957df5ed99"
       proved="true"
       expanded="false"
-      shape="CV5aNiltaConsVVainfix &gt;=V3c1Iainfix &gt;=amaxV8V4V1NIiainfix &lt;V9aprefix -V0Aainfix &lt;aprefix -V1V9ainfix =V8aprefix -V9iainfix &lt;=V9aprefix -V1ainfix &gt;=V8V1ainfix &lt;=V8V0Laminmaxado_moveV2V6ainfix -V3c1FIainfix &gt;=V3c1Iainfix &gt;=V3c1F">
+      shape="CV5aNiltaConsVVainfix &gt;=V3c1LamaxV9V0Iainfix &gt;=V9V1NLamaxV8V4Iiainfix &lt;V11aprefix -V0Aainfix &lt;aprefix -V1V11ainfix =V8aprefix -V11iainfix &lt;=V11aprefix -V1ainfix &gt;=V8V1ainfix &lt;=V8V0Laminmaxado_moveV2V6ainfix -V3c1FIainfix &gt;=V3c1Iainfix &gt;=V3c1F">
       <label
        name="expl:VC for negabeta_rec"/>
       <proof
@@ -748,10 +748,10 @@
       locfile="../alphaBeta.mlw"
       loclnum="139" loccnumb="7" loccnume="19"
       expl="5. postcondition"
-      sum="10414f5e5277a9840a5e359a8dcb15ba"
+      sum="ca0c6a051e227c935e565f6d8e34441c"
       proved="false"
       expanded="true"
-      shape="CV5aNiltaConsVViais_emptyV10ainfix =V9V4iainfix &lt;V11V1Aainfix &lt;V0V11ainfix =V9V11iainfix &lt;=V11V0ainfix &lt;=V9V0ainfix &gt;=V9V1LaminaTuple2V2V3V10LaelementsV5Iiais_emptyV12ainfix =V9amaxV8V4iainfix &lt;V13V1Aainfix &lt;amaxamaxV8V4V0V13ainfix =V9V13iainfix &lt;=V13amaxamaxV8V4V0ainfix &lt;=V9amaxamaxV8V4V0ainfix &gt;=V9V1LaminaTuple2V2V3V12LaelementsV7FIainfix &gt;=V3c1Iainfix &gt;=amaxV8V4V1NIiainfix &lt;V14aprefix -V0Aainfix &lt;aprefix -V1V14ainfix =V8aprefix -V14iainfix &lt;=V14aprefix -V1ainfix &gt;=V8V1ainfix &lt;=V8V0Laminmaxado_moveV2V6ainfix -V3c1FIainfix &gt;=V3c1Iainfix &gt;=V3c1F">
+      shape="CV5aNiltaConsVViais_emptyV12ainfix =V11V4iainfix &lt;V13V1Aainfix &lt;V0V13ainfix =V11V13iainfix &lt;=V13V0ainfix &lt;=V11V0ainfix &gt;=V11V1LaminaTuple2V2V3V12LaelementsV5Iiais_emptyV14ainfix =V11V9iainfix &lt;V15V1Aainfix &lt;V10V15ainfix =V11V15iainfix &lt;=V15V10ainfix &lt;=V11V10ainfix &gt;=V11V1LaminaTuple2V2V3V14LaelementsV7FIainfix &gt;=V3c1LamaxV9V0Iainfix &gt;=V9V1NLamaxV8V4Iiainfix &lt;V16aprefix -V0Aainfix &lt;aprefix -V1V16ainfix =V8aprefix -V16iainfix &lt;=V16aprefix -V1ainfix &gt;=V8V1ainfix &lt;=V8V0Laminmaxado_moveV2V6ainfix -V3c1FIainfix &gt;=V3c1Iainfix &gt;=V3c1F">
       <label
        name="expl:VC for negabeta_rec"/>
      </goal>
@@ -762,10 +762,10 @@
     locfile="../alphaBeta.mlw"
     loclnum="161" loccnumb="4" loccnume="14"
     expl="VC for alpha_beta"
-    sum="135b737fcae00f3ea665881526824bba"
+    sum="e238c2500fb35ff2eba38b72c1d2b903"
     proved="true"
     expanded="false"
-    shape="ainfix =V2aminmaxV0V1Iiainfix &lt;aminmaxV0V1ainfinityAainfix &lt;aprefix -ainfinityaminmaxV0V1ainfix =V2aminmaxV0V1iainfix &lt;=aminmaxV0V1aprefix -ainfinityainfix &lt;=V2aprefix -ainfinityainfix &gt;=V2ainfinityFAainfix &gt;=V1c0Iainfix &gt;=V1c0F">
+    shape="ainfix =V4aminmaxV0V1Iiainfix &lt;aminmaxV0V1V2Aainfix &lt;V3aminmaxV0V1ainfix =V4aminmaxV0V1iainfix &lt;=aminmaxV0V1V3ainfix &lt;=V4V3ainfix &gt;=V4V2FAainfix &gt;=V1c0Laprefix -ainfinityLainfinityIainfix &gt;=V1c0F">
     <label
      name="expl:VC for alpha_beta"/>
     <proof

examples/arm/why3session.xml

@@ -24,10 +24,10 @@
     locfile="../arm.mlw"
     loclnum="16" loccnumb="6" loccnume="20"
     expl="VC for insertion_sort"
-    sum="1aa1097194b9d30e0d6cf83318c97522"
+    sum="5677a170e9f6faf600b34c4281eebd63"
     proved="false"
     expanded="false"
-    shape="iainfix <=V5c10iainfix <agetV13V11agetV13ainfix -V11c1ainfix <V18V11Aainfix <=c0V11Aainfix <=ainfix *c2V15ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V18Aainvamk arrayV0V17Aainfix <=V18V5Aainfix <=c1V18Iainfix =V18ainfix -V11c1FIainfix =V17asetV16ainfix -V11c1agetV13V11Aainfix <=c0V0FAainfix <ainfix -V11c1V0Aainfix <=c0ainfix -V11c1Iainfix =V16asetV13V11agetV13ainfix -V11c1Aainfix <=c0V0FAainfix <V11V0Aainfix <=c0V11Aainfix <ainfix -V11c1V0Aainfix <=c0ainfix -V11c1Aainfix <V11V0Aainfix <=c0V11Iainfix =V15ainfix +V12c1Fainfix <ainfix -c10V19ainfix -c10V5Aainfix <=c0ainfix -c10V5Aainfix <=ainfix *c2V12ainfix *ainfix -V19c2ainfix -V19c1Aainfix =V10ainfix -V19c2AainvV14Aainfix <=V19c11Aainfix <=c2V19Iainfix =V19ainfix +V5c1FAainfix <V11V0Aainfix <=c0V11Aainfix <ainfix -V11c1V0Aainfix <=c0ainfix -V11c1Aainfix <=c0V0Iainfix <=ainfix *c2V12ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V11AainvV14Aainfix <=V11V5Aainfix <=c1V11Lamk arrayV0V13FAainfix <=ainfix *c2V6ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V5AainvV9Aainfix <=V5V5Aainfix <=c1V5Iainfix =V10ainfix +V7c1Fainfix <=V6c45Aainfix =V7c9Aainfix <=c0V0Iainfix <=ainfix *c2V6ainfix *ainfix -V5c2ainfix -V5c1Aainfix =V7ainfix -V5c2AainvV9Aainfix <=V5c11Aainfix <=c2V5Lamk arrayV0V8FAainfix <=ainfix *c2V1ainfix *ainfix -c2c2ainfix -c2c1Aainfix =V2ainfix -c2c2AainvV4Aainfix <=c2c11Aainfix <=c2c2Iainfix =V1c0Aainfix =V2c0AainvV4Aainfix <=c0V0Lamk arrayV0V3FF">
+    shape="iainfix <=V5c10iainfix <agetV13V11agetV13V15ainfix <V21V11Aainfix <=c0V11Aainfix <=ainfix *c2V16ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V21Aainvamk arrayV0V20Aainfix <=V21V5Aainfix <=c1V21Iainfix =V21ainfix -V11c1FIainfix =V20asetV18V19agetV13V11Aainfix <=c0V0FAainfix <V19V0Aainfix <=c0V19Lainfix -V11c1Iainfix =V18asetV13V11agetV13V17Aainfix <=c0V0FAainfix <V11V0Aainfix <=c0V11Aainfix <V17V0Aainfix <=c0V17Lainfix -V11c1Aainfix <V11V0Aainfix <=c0V11Iainfix =V16ainfix +V12c1Fainfix <ainfix -c10V22ainfix -c10V5Aainfix <=c0ainfix -c10V5Aainfix <=ainfix *c2V12ainfix *ainfix -V22c2ainfix -V22c1Aainfix =V10ainfix -V22c2AainvV14Aainfix <=V22c11Aainfix <=c2V22Iainfix =V22ainfix +V5c1FAainfix <V11V0Aainfix <=c0V11Aainfix <V15V0Aainfix <=c0V15Aainfix <=c0V0Lainfix -V11c1Iainfix <=ainfix *c2V12ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V11AainvV14Aainfix <=V11V5Aainfix <=c1V11Lamk arrayV0V13FAainfix <=ainfix *c2V6ainfix +ainfix *ainfix -V5c2ainfix -V5c1ainfix *c2ainfix -V5V5AainvV9Aainfix <=V5V5Aainfix <=c1V5Iainfix =V10ainfix +V7c1Fainfix <=V6c45Aainfix =V7c9Aainfix <=c0V0Iainfix <=ainfix *c2V6ainfix *ainfix -V5c2ainfix -V5c1Aainfix =V7ainfix -V5c2AainvV9Aainfix <=V5c11Aainfix <=c2V5Lamk arrayV0V8FAainfix <=ainfix *c2V1ainfix *ainfix -c2c2ainfix -c2c1Aainfix =V2ainfix -c2c2AainvV4Aainfix <=c2c11Aainfix <=c2c2Iainfix =V1c0Aainfix =V2c0AainvV4Aainfix <=c0V0Lamk arrayV0V3FF">
     <label
      name="expl:VC for insertion_sort"/>
    </goal>

examples/bellman_ford/bf_WP_BellmanFord_WP_parameter_bellman_ford_15.v

@@ -6,10 +6,11 @@ Require int.Int.
 Require map.Map.
 
 (* Why3 assumption *)
-Definition unit  := unit.
+Definition unit := unit.
 
 (* Why3 assumption *)
-Inductive list (a:Type) {a_WT:WhyType a} :=
+Inductive list
+  (a:Type) {a_WT:WhyType a} :=
   | Nil : list a
   | Cons : a -> (list a) -> list a.
 Axiom list_WhyType : forall (a:Type) {a_WT:WhyType a}, WhyType (list a).
@@ -18,7 +19,7 @@ Implicit Arguments Nil [[a] [a_WT]].
 Implicit Arguments Cons [[a] [a_WT]].
 
 (* Why3 assumption *)
-Fixpoint length {a:Type} {a_WT:WhyType a}(l:(list a)) {struct l}: Z :=
+Fixpoint length {a:Type} {a_WT:WhyType a} (l:(list a)) {struct l}: Z :=
   match l with
   | Nil => 0%Z
   | (Cons _ r) => (1%Z + (length r))%Z
@@ -37,15 +38,15 @@ Existing Instance set_WhyType.
 Parameter mem: forall {a:Type} {a_WT:WhyType a}, a -> (set a) -> Prop.
 
 (* Why3 assumption *)
-Definition infix_eqeq {a:Type} {a_WT:WhyType a}(s1:(set a)) (s2:(set
+Definition infix_eqeq {a:Type} {a_WT:WhyType a} (s1:(set a)) (s2:(set
   a)): Prop := forall (x:a), (mem x s1) <-> (mem x s2).
 
 Axiom extensionality : forall {a:Type} {a_WT:WhyType a}, forall (s1:(set a))
   (s2:(set a)), (infix_eqeq s1 s2) -> (s1 = s2).
 
 (* Why3 assumption *)
-Definition subset {a:Type} {a_WT:WhyType a}(s1:(set a)) (s2:(set a)): Prop :=
-  forall (x:a), (mem x s1) -> (mem x s2).
+Definition subset {a:Type} {a_WT:WhyType a} (s1:(set a)) (s2:(set
+  a)): Prop := forall (x:a), (mem x s1) -> (mem x s2).
 
 Axiom subset_refl : forall {a:Type} {a_WT:WhyType a}, forall (s:(set a)),
   (subset s s).
@@ -57,7 +58,7 @@ Axiom subset_trans : forall {a:Type} {a_WT:WhyType a}, forall (s1:(set a))
 Parameter empty: forall {a:Type} {a_WT:WhyType a}, (set a).
 
 (* Why3 assumption *)
-Definition is_empty {a:Type} {a_WT:WhyType a}(s:(set a)): Prop :=
+Definition is_empty {a:Type} {a_WT:WhyType a} (s:(set a)): Prop :=
   forall (x:a), ~ (mem x s).
 
 Axiom empty_def1 : forall {a:Type} {a_WT:WhyType a}, (is_empty (empty :(set
@@ -136,7 +137,7 @@ Parameter vertices: (set vertex).
 Parameter edges: (set (vertex* vertex)%type).
 
 (* Why3 assumption *)
-Definition edge(x:vertex) (y:vertex): Prop := (mem (x, y) edges).
+Definition edge (x:vertex) (y:vertex): Prop := (mem (x, y) edges).
 
 Axiom edges_def : forall (x:vertex) (y:vertex), (mem (x, y) edges) -> ((mem x
   vertices) /\ (mem y vertices)).
@@ -148,7 +149,7 @@ Axiom s_in_graph : (mem s vertices).
 Axiom vertices_cardinal_pos : (0%Z < (cardinal vertices))%Z.
 
 (* Why3 assumption *)
-Fixpoint infix_plpl {a:Type} {a_WT:WhyType a}(l1:(list a)) (l2:(list
+Fixpoint infix_plpl {a:Type} {a_WT:WhyType a} (l1:(list a)) (l2:(list
   a)) {struct l1}: (list a) :=
   match l1 with
   | Nil => l2
@@ -167,7 +168,8 @@ Axiom Append_length : forall {a:Type} {a_WT:WhyType a}, forall (l1:(list a))
   l2)) = ((length l1) + (length l2))%Z).
 
 (* Why3 assumption *)
-Fixpoint mem1 {a:Type} {a_WT:WhyType a}(x:a) (l:(list a)) {struct l}: Prop :=
+Fixpoint mem1 {a:Type} {a_WT:WhyType a} (x:a) (l:(list
+  a)) {struct l}: Prop :=
   match l with