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vidjil
vidjil
Commits
c12f4e49
Commit
c12f4e49
authored
Aug 28, 2017
by
Mathieu Giraud
Browse files
Makefile: add 'lib/unbam' in release
parent
f4f98c58
Changes
1
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Makefile
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c12f4e49
...
...
@@ -155,7 +155,7 @@ cleanall: clean
RELEASE_TAG
=
"notag"
RELEASE_H
=
$(VIDJIL_ALGO_SRC)
/release.h
RELEASE_SOURCE
=
$(
wildcard
$(VIDJIL_ALGO_SRC)
/
*
.cpp
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/
*
.h
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/core/
*
.cpp
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/core/
*
.hpp
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/tests/unit-tests/
*
.cpp
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/core/
*
.h
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/tests/unit-tests/
*
.h
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/cgi/
*
.cpp
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/lib/
*
.cpp
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/lib/
*
.h
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/lib/
*
.hpp
)
$(
wildcard
tools/
*
.py
)
RELEASE_SOURCE
=
$(
wildcard
$(VIDJIL_ALGO_SRC)
/
*
.cpp
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/
*
.h
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/core/
*
.cpp
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/core/
*
.hpp
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/tests/unit-tests/
*
.cpp
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/core/
*
.h
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/tests/unit-tests/
*
.h
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/cgi/
*
.cpp
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/lib/
*
.cpp
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/lib/
*
.h
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/lib/
*
.hpp
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/lib/unbam/
*
.c
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/lib/unbam/
*
.h
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/lib/unbam/Makefile
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/lib/unbam/LICENSE
)
$(
wildcard
tools/
*
.py
)
RELEASE_MAKE
=
./Makefile
$(VIDJIL_ALGO_SRC)
/Makefile
$(VIDJIL_ALGO_SRC)
/core/Makefile
$(VIDJIL_ALGO_SRC)
/tests/Makefile
$(VIDJIL_ALGO_SRC)
/lib/Makefile germline/Makefile data/Makefile tools/tests/Makefile doc/Makefile
RELEASE_TESTS
=
doc/format-analysis.org data/get-sequences
$(
wildcard
data/
*
.vidjil
)
$(
wildcard
data/
*
.analysis
)
$(
wildcard
data/
*
.g
)
$(
wildcard
data/
*
.fa
)
$(
wildcard
data/
*
.fq
)
$(VIDJIL_ALGO_SRC)
/tests/repseq_vdj.py
$(VIDJIL_ALGO_SRC)
/tests/should-vdj-to-tap.py
$(VIDJIL_ALGO_SRC)
/tests/ansi.py
$(
wildcard
$(VIDJIL_ALGO_SRC)
/tests/should-vdj-tests/
*
.should-vdj.fa
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/tests/should-vdj-tests/
*
.should-locus.fa
)
$(VIDJIL_ALGO_SRC)
/tests/should-to-tap.sh
$(
wildcard
$(VIDJIL_ALGO_SRC)
/tests/should-get-tests/
*
.should-get
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/tests/bugs/
*
.fa
)
$(
wildcard
$(VIDJIL_ALGO_SRC)
/tests/bugs/
*
.should-get
)
$(VIDJIL_ALGO_SRC)
/tests/format-json.sh
$(
wildcard
doc/analysis-example.vidjil
)
$(
wildcard
tools/tests/
*
.should_get
)
tools/tests/should-to-tap.sh tools/diff_json.sh
RELEASE_GERMLINES
=
germline/germline_id germline/get-saved-germline germline/get-germline germline/split-from-imgt.py
$(
wildcard
germline/
*
.g
)
germline/revcomp-fasta.py germline/fasta.py
...
...
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