Skip to content
GitLab
Projects
Groups
Snippets
Help
Loading...
Help
What's new
7
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
Open sidebar
vidjil
vidjil
Commits
8d64f661
Commit
8d64f661
authored
Nov 23, 2016
by
HERBERT Ryan
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
controllers/sample_set.py failsafe for page
parent
1ee9795a
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
1 addition
and
0 deletions
+1
-0
server/web2py/applications/vidjil/controllers/sample_set.py
server/web2py/applications/vidjil/controllers/sample_set.py
+1
-0
No files found.
server/web2py/applications/vidjil/controllers/sample_set.py
View file @
8d64f661
...
...
@@ -176,6 +176,7 @@ def all():
# failsafe if filtered display all results
step
=
len
(
list
)
if
step
is
None
else
step
page
=
0
if
page
is
None
else
page
factory
=
ModelFactory
()
helper
=
factory
.
get_instance
(
type
=
type
)
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment