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vidjil
vidjil
Commits
87dbfd0d
Commit
87dbfd0d
authored
Jul 11, 2019
by
Mathieu Giraud
Browse files
Merge branch 'feature-a/update-repseq-vdj-for-mixcr' into 'dev'
Update repseq_vdj for mixcr See merge request
!495
parents
dc8209bd
d962a3e8
Pipeline
#86738
passed with stages
in 6 minutes and 9 seconds
Changes
1
Pipelines
1
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Inline
Side-by-side
algo/tests/repseq_vdj.py
View file @
87dbfd0d
...
...
@@ -92,6 +92,9 @@ class Result(VDJ_Formatter):
self
.
populate
()
def
__contains__
(
self
,
key
):
return
key
in
self
.
d
def
__getitem__
(
self
,
key
):
return
self
.
d
[
key
]
...
...
@@ -155,16 +158,20 @@ class MiXCR_Result(Result):
return
None
def
populate
(
self
):
self
.
vdj
[
V
]
=
[
self
[
'
B
est
V h
it'
]]
if
self
[
'
B
est
D h
it'
]:
self
.
vdj
[
D
]
=
[
self
[
'
B
est
D h
it'
]]
self
.
vdj
[
J
]
=
[
self
[
'
B
est
J h
it'
]]
self
.
vdj
[
V
]
=
[
self
[
'
b
est
VH
it'
]]
if
self
[
'
b
est
DH
it'
]:
self
.
vdj
[
D
]
=
[
self
[
'
b
est
DH
it'
]]
self
.
vdj
[
J
]
=
[
self
[
'
b
est
JH
it'
]]
self
.
vdj
[
N1
]
=
self
[
'N. Seq. VDJunction'
]
self
.
vdj
[
N2
]
=
self
[
'N. Seq. DJJunction'
]
self
.
vdj
[
N
]
=
self
[
'N. Seq. VJJunction'
]
if
'nSeqVDJunction'
in
self
:
self
.
vdj
[
N1
]
=
self
[
'nSeqVDJunction'
]
if
'nSeqDJJunction'
in
self
:
self
.
vdj
[
N2
]
=
self
[
'nSeqDJJunction'
]
if
'nSeqVJJunction'
in
self
:
self
.
vdj
[
N
]
=
self
[
'nSeqVJJunction'
]
self
.
vdj
[
JUNCTION
]
=
self
[
'AA. Seq. CDR3'
]
if
'aaSeqCDR3'
in
self
:
self
.
vdj
[
JUNCTION
]
=
self
[
'aaSeqCDR3'
]
def
header_mixcr_results
(
ff_mixcr
):
...
...
@@ -172,12 +179,12 @@ def header_mixcr_results(ff_mixcr):
f
=
open
(
ff_mixcr
).
__iter__
()
mixcr_first_line
=
f
.
next
()
globals
()[
'mixcr_labels'
]
=
mixcr_first_line
.
split
(
'
\t
'
)
globals
()[
'mixcr_labels'
]
=
mixcr_first_line
.
rstrip
().
split
(
'
\t
'
)
while
True
:
l
=
f
.
next
()
l
=
f
.
next
()
.
rstrip
()
result
=
MiXCR_Result
(
l
)
yield
result
[
'
D
escr
iption
R1'
],
result
.
to_vdj
()
yield
result
[
'
d
escr
s
R1'
],
result
.
to_vdj
()
...
...
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