Commit a2dde48a authored by CLAUDEPIERRE Ludovic's avatar CLAUDEPIERRE Ludovic
Browse files

màj address 2 bytes

parent 8b0a7dc1
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.03.2020 10:08:11
-- Design Name:
-- Module Name: traitor_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use work.triggy_common.all;
use work.common.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity traitor_tb is
Port (
clk_100 : out STD_LOGIC;
Dswitch : out STD_LOGIC_VECTOR(1 downto 0);
stm_trig: out STD_LOGIC;
trig_delay_in: out trig_delays;
trig_width_in : out trig_widths;
trig_amplitude_in : out STD_LOGIC_VECTOR(7 downto 0);
-- OUPUT--
led : in STD_LOGIC_VECTOR (15 downto 0);
Fault_trig_out : in STD_LOGIC;
clk_init : in STD_LOGIC;
clk_dphase : in STD_LOGIC;
clk_XOR_out : in STD_LOGIC;
clk_fault_out : in STD_LOGIC;
clk_fault_out2 : in STD_LOGIC );
end traitor_tb;
architecture Behavioral of traitor_tb is
--// input to the glitchy module
signal s_clk_100 : STD_LOGIC:='0';
signal s_Dswitch : STD_LOGIC_VECTOR(1 downto 0):="00";
signal s_stm_trig : STD_LOGIC:='0';
signal s_delay : trig_delays;
signal s_width : trig_widths;
signal s_amplitude : STD_LOGIC_VECTOR(7 downto 0):=x"e0";
--// output from the glitchy module
signal s_led : STD_LOGIC_VECTOR (15 downto 0):=x"0000";
signal s_Fault_trig_out : STD_LOGIC;
signal s_clk_init : STD_LOGIC;
signal s_clk_dphase : STD_LOGIC;
signal s_clk_XOR_out : STD_LOGIC;
signal s_clk_fault_out : STD_LOGIC;
signal s_clk_fault_out2 : STD_LOGIC;
signal s_rst : STD_LOGIC :='0';
constant T100 : time := 10 ns;
constant Trst : time := 500 ns;
constant Twait : time := 100 ns;
begin
UUT : entity work.mmcm_reset
port map (
clk_100 => s_clk_100,
Dswitch => s_Dswitch,
stm_trig => s_stm_trig,
trig_delay_in =>s_delay ,
trig_width_in=>s_width ,
trig_amplitude_in=> s_amplitude,
-- OUPUT--
led => s_led,
Fault_trig_out => s_Fault_trig_out ,
clk_init => s_clk_init ,
clk_dphase=> s_clk_dphase,
clk_XOR_out => s_clk_XOR_out,
clk_fault_out => s_clk_fault_out,
clk_fault_out2 => s_clk_fault_out2
);
tb_clock100 : process
begin
s_clk_100 <= '0';
wait for T100/2;
s_clk_100 <= '1';
wait for T100/2;
end process;
s_stm_trig <= '0', '1' after 1*T100+0.25*T100+Trst;
s_rst <= '0', '1' after 5*T100, '0' after 7*T100;
remplissage_trigconf : process(s_rst)
begin
if rising_edge(s_rst) then
s_delay(0) <= x"00000007";
s_width(0) <= x"00000005";
for i in 1 to NB_TRIGGERS-1 loop
s_delay(i) <= x"00000000";
s_width(i) <= x"00000000";
end loop;
end if;
end process;
end Behavioral;
......@@ -178,15 +178,14 @@ stm_evt<=(stm_trig_b xor stm_trig_b2) and stm_trig_b ;
MMCME2_ADV_inst : MMCME2_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW)
CLKFBOUT_MULT_F => 10.0, -- Multiply value for all CLKOUT (2.000-64.000).
CLKFBOUT_MULT_F => 10.0, -- Multiply value for all CLKOUT (2.000-64.000). (pour 24MHz : 12.0, pour 8MHz : 10)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => 10.0,
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128)
--CLKOUT0_DIVIDE => 100,
CLKOUT1_DIVIDE => 125, CLKOUT2_DIVIDE => 125, CLKOUT3_DIVIDE => 1, CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1, CLKOUT6_DIVIDE => 1, CLKOUT0_DIVIDE_F => 125.000, -- Divide amount for CLKOUT0 (1.000-128.000).
CLKOUT1_DIVIDE => 125, CLKOUT2_DIVIDE => 1, CLKOUT3_DIVIDE => 1, CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1, CLKOUT6_DIVIDE => 1, CLKOUT0_DIVIDE_F => 125.000, -- pour 24MHz : 50 ; pour 8 MHz : 125)
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT1_DUTY_CYCLE => 0.5, CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5, CLKOUT4_DUTY_CYCLE => 0.5, CLKOUT5_DUTY_CYCLE => 0.5,
......@@ -382,6 +381,7 @@ begin
when "01" => s_led <= std_logic_vector(trig_delay_in(1)(15 downto 0)); -- address : 9
when "10" => s_led <= std_logic_vector(trig_delay_in(2)(15 downto 0)); -- address : 11
when "11" => s_led <= std_logic_vector(trig_delay_in(3)(15 downto 0)); -- address : 19
when others => s_led <= x"0000";
end case;
end if;
end process;
......
......@@ -52,7 +52,9 @@ architecture behavior of configuration_manager is
signal mem: std_logic_vector(MAX_ADDRESS*8-1 downto 0);
-- signal address: unsigned(7 downto 0);
signal v_address: std_logic_vector(15 downto 0);
signal address: integer range 0 to 255;
signal count_add: integer range 0 to 255;
signal crw: std_logic; -- 0 read 1 write
signal autoread_enable: std_logic;
......@@ -83,18 +85,8 @@ begin
end loop;
end process;
-- uart_conf_seq: for i in 0 to SEQUENCE_SIZE-1 generate
-- uart_trig_conf_seq(i) <= mem((UART_INTERCEPT_SEQ_ADD+i)*8 + 7 downto (UART_INTERCEPT_SEQ_ADD+i)*8);
-- end generate;
-- uart_trig_conf <= ( sequence => uart_trig_conf_seq,
-- sequence_size => unsigned(mem(UART_INTERCEPT_SEQ_SIZE_ADD*8 + 7 downto UART_INTERCEPT_SEQ_SIZE_ADD*8)));
-- apdu follower conf
-- apdu_head: for i in 0 to APDU_FOLLOWER_HEADER_SELECT_SIZE-1 generate
-- apdu_header(i) <= mem((APDU_FOLLOWER_HEADER_SELECT_ADD+i)*8 + 7 downto (APDU_FOLLOWER_HEADER_SELECT_ADD+i)*8);
-- end generate;
address <= to_integer(unsigned(v_address));
-- mem operations
read_fifo: fifo_autoreader
......@@ -133,7 +125,7 @@ begin
if command_state = SEND_CHECKSUM then
checksum <= X"00";
elsif data_en = '1' then
checksum <= checksum xor data_byte;
checksum <= v_address(7 downto 0);-- checksum xor data_byte;
end if;
end if;
end process;
......@@ -159,16 +151,21 @@ begin
add_set: process(clk, reset)--write data to host
begin
if reset = '1' then
address <= 0;
v_address <= x"0000";
elsif rising_edge(clk) then
if command_state = ADD and data_en = '1' then
address <= to_integer(unsigned(data_byte));
count_add<=count_add+1;
if count_add <2 then
v_address((2-count_add)*8-1 downto (2-count_add-1)*8) <= data_byte; -- SIZE ADRESS = 2 BYTES
end if;
elsif command_state = FUN then
count_add <=0;
end if;
end if;
end process;
fsm_command: process(clk, reset)
fsm_command: process(clk, reset,count_add)
begin
if reset = '1' then
command_state <= FUN;
......@@ -202,7 +199,7 @@ begin
end if;
when ADD =>
if data_en = '1' then
if data_en = '1' and count_add>1 then
if crw = '1' then --write mode expect data value
command_state <= READ_DATA;
else
......
......@@ -13,7 +13,7 @@ package triggy_common is
constant TRIGGERS_ADD: Integer := STATE_ADD+STATE_SIZE;--1
constant TRIGGER_CONF_SIZE: Integer := 9;-- 17;
constant NB_TRIGGERS: Integer := 20;
constant NB_TRIGGERS: Integer := 64;
-- constant APDU_FOLLOWER_CONFIG_ADD: Integer := TRIGGERS_ADD+TRIGGER_CONF_SIZE*NB_TRIGGERS;-- 1+9*4 //--1+17*4=69
-- constant APDU_FOLLOWER_CONFIG_SIZE: Integer := 1;
......
......@@ -18,7 +18,6 @@
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="SimulatorLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
......@@ -26,27 +25,27 @@
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableCoreContainer" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTXSimLaunchSim" Val="29"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="1"/>
<Option Name="WTModelSimExportSim" Val="1"/>
<Option Name="WTQuestaExportSim" Val="1"/>
<Option Name="WTIesExportSim" Val="1"/>
<Option Name="WTVcsExportSim" Val="1"/>
<Option Name="WTRivieraExportSim" Val="1"/>
<Option Name="WTActivehdlExportSim" Val="1"/>
<Option Name="WTXSimExportSim" Val="4"/>
<Option Name="WTModelSimExportSim" Val="4"/>
<Option Name="WTQuestaExportSim" Val="4"/>
<Option Name="WTIesExportSim" Val="4"/>
<Option Name="WTVcsExportSim" Val="4"/>
<Option Name="WTRivieraExportSim" Val="4"/>
<Option Name="WTActivehdlExportSim" Val="4"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
......@@ -61,6 +60,24 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/ip/fifo.xcix">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../Projet_USB/UART-write/UART_com.srcs/sources_1/ip/fifo.xcix"/>
<Attr Name="ImportTime" Val="1582035536"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/fifo/fifo.xci">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../Projet_USB/UART-write/UART_com.srcs/sources_1/ip/fifo/fifo.xci"/>
<Attr Name="ImportTime" Val="1580896726"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/common.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
......@@ -143,7 +160,6 @@
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="triggy_glitch"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
......@@ -157,49 +173,51 @@
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/imports/PLL_demo_PIN/Arty_Master.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="triggy_glitch"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo">
<File Path="$PSRCDIR/sources_1/ip/fifo.xcix">
<File Path="$PSRCDIR/sources_1/common.vhd">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../Projet_USB/UART-write/UART_com.srcs/sources_1/ip/fifo.xcix"/>
<Attr Name="ImportTime" Val="1582035536"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/fifo/fifo.xci">
<File Path="$PSRCDIR/sources_1/triggy_common.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/PLL_clk_PbMUX.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/traitor_tb.vhd">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../Projet_USB/UART-write/UART_com.srcs/sources_1/ip/fifo/fifo.xci"/>
<Attr Name="ImportTime" Val="1580896726"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="fifo"/>
<Option Name="UseBlackboxStub" Val="1"/>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="traitor_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SimMode" Val="post-synthesis"/>
<Option Name="SrcSet" Val=""/>
<Option Name="NLNetlistMode" Val="funcsim"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
......@@ -237,15 +255,6 @@
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="fifo_synth_1" Type="Ft3:Synth" SrcSet="fifo" Part="xc7a35tcsg324-1" ConstrsSet="fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
......@@ -257,28 +266,14 @@
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
<Step Id="write_bitstream">
<Option Id="BinFile">1</Option>
</Step>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="fifo_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<Board/>
<DashboardSummary Version="1" Minor="0">
......@@ -304,6 +299,7 @@
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
<GadgetParam Name="VIEW.TYPE" Type="string" Value="graph"/>
</Gadget>
</Gadgets>
</Dashboard>
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment