Commit 94b2d16a authored by CLAUDEPIERRE Ludovic's avatar CLAUDEPIERRE Ludovic
Browse files

ajout d'une ILA pour observation des signaux en lecture UART

parent eca0cc44
......@@ -25,6 +25,19 @@ end configuration_manager;
architecture behavior of configuration_manager is
component ila_0 IS
PORT(
clk : in STD_LOGIC; -- clk
probe0 : in STD_LOGIC_VECTOR (2 downto 0); -- state
probe1 : in STD_LOGIC_VECTOR (0 downto 0); -- read_en
probe2 : in STD_LOGIC_VECTOR (15 downto 0); -- v_address
probe3 : in STD_LOGIC_VECTOR (7 downto 0); -- databyte
probe4 : in STD_LOGIC_VECTOR (3 downto 0); --countadd
probe5 : in STD_LOGIC_VECTOR (0 downto 0) --crw
);
end component;
component fifo_autoreader is
port(clk: in std_logic;
reset: in std_logic;
......@@ -53,9 +66,13 @@ architecture behavior of configuration_manager is
-- signal address: unsigned(7 downto 0);
signal v_address: std_logic_vector(15 downto 0);
signal v_state: std_logic_vector(2 downto 0);
signal address: integer range 0 to 255;
signal count_add: integer range 0 to 255;
signal crw: std_logic; -- 0 read 1 write
signal v_count_add: std_logic_vector(3 downto 0); -- 0 read 1 write
signal v_crw: std_logic_vector(0 downto 0); -- 0 read 1 write
signal v_data_en: std_logic_vector(0 downto 0); -- 0 read 1 write
signal autoread_enable: std_logic;
......@@ -71,7 +88,8 @@ architecture behavior of configuration_manager is
dout <= dout_buf;
dout_write <= dout_write_order;
autoread_enable <= '1';
v_data_en(0)<=data_en;
v_crw(0)<=crw;
-- Memory mapping
--triggers confs
......@@ -86,6 +104,7 @@ begin
end process;
v_count_add <= std_logic_vector(to_unsigned(count_add,4));
address <= to_integer(unsigned(v_address));
-- mem operations
......@@ -102,7 +121,18 @@ address <= to_integer(unsigned(v_address));
data_en => data_en
);
ila : ila_0
port map(
clk => clk,
probe0 => v_state,
probe1 => v_data_en,
probe2 => v_address,--packet2send,
probe3 => data_byte,
probe4 => v_count_add,
probe5 => v_crw
);
update_mem: process(clk, reset)
begin
if reset = '1' then
......@@ -173,6 +203,7 @@ address <= to_integer(unsigned(v_address));
elsif rising_edge(clk) then
case command_state is
when FUN =>
v_state<="000";
if data_en = '1' then -- read function
if data_byte = X"00" then
crw <= '0';
......@@ -192,6 +223,7 @@ address <= to_integer(unsigned(v_address));
end if;
when TRIG_IMM =>
v_state<="111";
if data_en = '1' then
command_state <= SEND_CHECKSUM;
else
......@@ -199,6 +231,7 @@ address <= to_integer(unsigned(v_address));
end if;
when ADD =>
v_state<="001";
if data_en = '1' and count_add>1 then
if crw = '1' then --write mode expect data value
command_state <= READ_DATA;
......@@ -210,6 +243,7 @@ address <= to_integer(unsigned(v_address));
end if;
when READ_DATA => -- read data from host and write to mem
v_state<="010";
if data_en = '1' then
command_state <= SEND_CHECKSUM;
else
......@@ -217,13 +251,16 @@ address <= to_integer(unsigned(v_address));
end if;
when WRITE_DATA => -- write data to host
v_state<="011";
command_state <= WAIT1;
when WAIT1 =>
v_state<="100";
command_state <= SEND_CHECKSUM;
when SEND_CHECKSUM =>
v_state<="101";
command_state <= FUN;
end case;
......
......@@ -39,13 +39,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="4"/>
<Option Name="WTModelSimExportSim" Val="4"/>
<Option Name="WTQuestaExportSim" Val="4"/>
<Option Name="WTIesExportSim" Val="4"/>
<Option Name="WTVcsExportSim" Val="4"/>
<Option Name="WTRivieraExportSim" Val="4"/>
<Option Name="WTActivehdlExportSim" Val="4"/>
<Option Name="WTXSimExportSim" Val="6"/>
<Option Name="WTModelSimExportSim" Val="6"/>
<Option Name="WTQuestaExportSim" Val="6"/>
<Option Name="WTIesExportSim" Val="6"/>
<Option Name="WTVcsExportSim" Val="6"/>
<Option Name="WTRivieraExportSim" Val="6"/>
<Option Name="WTActivehdlExportSim" Val="6"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
......@@ -220,6 +220,26 @@
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="ila_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_0">
<File Path="$PSRCDIR/sources_1/ip/ila_0.xcix">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/ila_0/ila_0.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="ila_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
......@@ -255,6 +275,17 @@
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="ila_0_synth_1" Type="Ft3:Synth" SrcSet="ila_0" Part="xc7a35tcsg324-1" ConstrsSet="ila_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
......@@ -274,6 +305,24 @@
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="ila_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="ila_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<Board/>
<DashboardSummary Version="1" Minor="0">
......
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