Commit 8b0a7dc1 authored by CLAUDEPIERRE Ludovic's avatar CLAUDEPIERRE Ludovic
Browse files

ajout fonctionnel du nombre de cycle d'horloge à glicher à entrer en UART aux...

ajout fonctionnel du nombre de cycle d'horloge à glicher à entrer en UART aux adresses 5+N*8. Noter que si on veut des valeurs supérieures à ff, il faut passer au byte supérieure. Exemple : pour un nombre de cycles égal à 12f2, il faut entrer f2 dans le byte 5 et 12 dans le byte 6.
parent 0a63f962
......@@ -128,6 +128,7 @@ architecture Behavioral of mmcm_reset is
shared variable Dcount : integer :=0;
shared variable kfault: Integer := 0;
shared variable delayfault: Integer := 0;
shared variable widthfault: Integer := 0;
signal stm_trig_b : std_logic := '0';
signal stm_trig_b2 : std_logic := '0';
......@@ -145,11 +146,9 @@ begin
--s_led<=Dcount_led(15 downto 0) when (Dswitch = "00") else Delay1(15 downto 0) when (Dswitch = "01") else Delay2(15 downto 0) when (Dswitch = "10") else Delay3(15 downto 0) when (Dswitch = "11");
led <= s_led(15 downto 0);
clk_fault_out <= clk_fault;
clk_fault_out2 <= clk_notfault;
clk_XOR_out <= clk_notXOR;
--clk_nXOR_out <= clk_notXOR;
clk_fault_out2 <= clk_fault;
clk_XOR_out <= clk_XOR;
clk_XOR<= (clk_0 xor clk_1) and clk_0;
clk_notXOR<= not(clk_0 xor clk_1) and not(clk_1);
......@@ -164,17 +163,8 @@ clk_fault <= clk_XOR when (Fault_trig='1') else clk_0;
clk_notfault <= clk_notXOR when (Fault_trig='1') else clk_0;
s_PSCLK<=clk_0;
--NFault<="10";
--//-------chargement des Delay de enregitrés en mémoire----------//
--Delay1<=std_logic_vector(trig_delay_in(0)(31 downto 0));
--Delay2<=std_logic_vector(trig_delay_in(1)(31 downto 0));
--Delay3<=std_logic_vector(trig_delay_in(2)(31 downto 0));
--Delay4<=std_logic_vector(trig_delay_in(3)(31 downto 0));
--//--------------------------------------------------------------//
-- rising edge buttons
--phplus<=(btn_phplus_b xor btn_phplus_b2) and btn_phplus_b ;
--phmoins<=(btn_phmoins_b xor btn_phmoins_b2) and btn_phmoins_b ;
Dplus<=(btn_Dplus_b xor btn_Dplus_b2) and btn_Dplus_b ;
Dmoins<=(btn_Dmoins_b xor btn_Dmoins_b2) and btn_Dmoins_b ;
......@@ -195,49 +185,30 @@ stm_evt<=(stm_trig_b xor stm_trig_b2) and stm_trig_b ;
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128)
--CLKOUT0_DIVIDE => 100,
CLKOUT1_DIVIDE => 125,
CLKOUT2_DIVIDE => 125,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 125.000, -- Divide amount for CLKOUT0 (1.000-128.000).
CLKOUT1_DIVIDE => 125, CLKOUT2_DIVIDE => 125, CLKOUT3_DIVIDE => 1, CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1, CLKOUT6_DIVIDE => 1, CLKOUT0_DIVIDE_F => 125.000, -- Divide amount for CLKOUT0 (1.000-128.000).
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT1_DUTY_CYCLE => 0.5, CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5, CLKOUT4_DUTY_CYCLE => 0.5, CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT0_PHASE => 0.0, CLKOUT1_PHASE => 0.0, CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0, CLKOUT4_PHASE => 0.0, CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-106)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
REF_JITTER1 => 0.0, REF_JITTER2 => 0.0,
STARTUP_WAIT => FALSE, -- Delays DONE until MMCM is locked (FALSE, TRUE)
-- Spread Spectrum: Spread Spectrum Attributes
SS_EN => "FALSE", -- Enables spread spectrum (FALSE, TRUE)
SS_MODE => "CENTER_HIGH", -- CENTER_HIGH, CENTER_LOW, DOWN_HIGH, DOWN_LOW
SS_MOD_PERIOD => 10000, -- Spread spectrum modulation period (ns) (VALUES)
-- USE_FINE_PS: Fine phase shift enable (TRUE/FALSE)
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_USE_FINE_PS => TRUE,
CLKOUT2_USE_FINE_PS => FALSE,
CLKOUT3_USE_FINE_PS => FALSE,
CLKOUT4_USE_FINE_PS => FALSE,
CLKOUT5_USE_FINE_PS => FALSE,
CLKOUT6_USE_FINE_PS => FALSE
CLKFBOUT_USE_FINE_PS => FALSE, CLKOUT0_USE_FINE_PS => FALSE, CLKOUT1_USE_FINE_PS => TRUE,
CLKOUT2_USE_FINE_PS => FALSE, CLKOUT3_USE_FINE_PS => FALSE, CLKOUT4_USE_FINE_PS => FALSE,
CLKOUT5_USE_FINE_PS => FALSE, CLKOUT6_USE_FINE_PS => FALSE
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
......@@ -268,7 +239,6 @@ stm_evt<=(stm_trig_b xor stm_trig_b2) and stm_trig_b ;
CLKINSEL => '1',
PWRDWN => '0', -- 1-bit input: Power-down
RST => rst, -- 1-bit input: Reset
-- DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports
DCLK => clk_0, -- 1-bit input: DRP clock
DO => DO, -- 16-bit output: DRP data
......@@ -278,8 +248,6 @@ stm_evt<=(stm_trig_b xor stm_trig_b2) and stm_trig_b ;
DEN => DEN, -- 1-bit input: DRP enable
DI => DI, -- 16-bit input: DRP data
DWE => DWE, -- 1-bit input: DRP write enable
-- Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs
PSCLK => s_PSCLK,
PSEN => s_PSEN,
......@@ -311,7 +279,6 @@ if rising_edge(s_PSCLK) then
case state is
when state_wait =>
if AGlitch>AGlitch_loc then
diffGlitch<=AGlitch-AGlitch_loc;
flagphplus<='1';
......@@ -354,17 +321,6 @@ if rising_edge(s_PSCLK) then
end if;
end process;
--btnPhase_event: process(clk_0)
--begin
-- if rising_edge(clk_0) then
-- btn_phplus_b2<=btn_phplus_b;
-- btn_phplus_b<=btn_phplus;
-- btn_phmoins_b2<=btn_phmoins_b;
-- btn_phmoins_b<=btn_phmoins;
-- end if;
--end process;
--/------------------ Paramétrisation du DelayN --------------------------/--
......@@ -382,15 +338,25 @@ begin
if Fault_flag='1' or stm_evt='1' then
if kfault<Nfault then
delayfault:=to_integer(trig_delay_in(kfault));
widthfault := to_integer(trig_width_in(kfault));
if widthfault = 0 then
widthfault := 1; -- si on oublie de remplir le nombre de cycle fauté, on glitch par défaut 1 seule fois
end if;
if delayfault = 0 then
kfault:=kfault+1; -- si le kème delay est nul, on passe à la faute suivante (balayage de toute la mémoire)
Fault_trig<='0';
Fault_flag<='1';
elsif Dcount = delayfault then
elsif Dcount >= delayfault and Dcount < delayfault+widthfault then
Fault_trig<='1';
Dcount:=Dcount+1;
Fault_flag<='1';
-- kfault:=kfault+1;
elsif Dcount = delayfault+widthfault then
Fault_trig<='0';
Dcount:=Dcount+1;
Fault_flag<='1';
kfault:=kfault+1;
else
Fault_trig<='0';
......
......@@ -133,42 +133,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/sources_1/imports/sources_1/imports/src/fifo_autoreader.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="ImportPath" Val="$PPRDIR/../../Projet_USB/UART-write/UART_com.srcs/sources_1/imports/sources_1/imports/src/fifo_autoreader.vhd"/>
<Attr Name="ImportTime" Val="1582028408"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/sources_1/imports/sources_1/imports/src/common.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="ImportPath" Val="$PPRDIR/../../Projet_USB/UART-write/UART_com.srcs/sources_1/imports/sources_1/imports/src/common.vhd"/>
<Attr Name="ImportTime" Val="1582028408"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/sources_1/imports/sources_1/imports/src/triggy_common.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="ImportPath" Val="$PPRDIR/../../Projet_USB/UART-write/UART_com.srcs/sources_1/imports/sources_1/imports/src/triggy_common.vhd"/>
<Attr Name="ImportTime" Val="1582035802"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/sources_1/imports/sources_1/imports/src/uart_ctrl_pkg.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="ImportPath" Val="$PPRDIR/../../Projet_USB/UART-write/UART_com.srcs/sources_1/imports/sources_1/imports/src/uart_ctrl_pkg.vhd"/>
<Attr Name="ImportTime" Val="1582028408"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/uart_ctrl_pkg.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
......@@ -266,9 +230,7 @@
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
......@@ -277,9 +239,7 @@
</Run>
<Run Id="fifo_synth_1" Type="Ft3:Synth" SrcSet="fifo" Part="xc7a35tcsg324-1" ConstrsSet="fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
......@@ -288,9 +248,7 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
......@@ -307,9 +265,7 @@
</Run>
<Run Id="fifo_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
......
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