Commit 5fd97c38 authored by RILLING Louis's avatar RILLING Louis
Browse files

Try nicely to fix links in qemu.org

parent cdf79a89
Pipeline #154547 passed with stages
in 3 minutes and 55 seconds
......@@ -71,14 +71,13 @@
- ld/store helper calls ~io_readx~/~io_writex~ if the ~tlb_addr~ is flagged as an MMIO region: e.g [[https://github.com/qemu/qemu/blob/v4.2.0/accel/tcg/cputlb.c#L1715-L1718]]
+ Now the final magic principle: load/store from/to MMIO regions always lead to a TLB cache miss. How?
- The TLB is initially empty.
- In the load/store slow path, ~load_helper~ / ~store_helper~ insert an
entry in the TLB: [[https://github.com/qemu/qemu/blob/v4.2.0/accel/tcg/cputlb.c#L1682-L1691]]
+ [[https://github.com/qemu/qemu/blob/v4.2.0/accel/tcg/cputlb.c#L895-L912][~tlb_fill~]] (generic) calls [[https://github.com/qemu/qemu/blob/v4.2.0/target/i386/excp_helper.c#L676-L702][~x86_cpu_tlb_fill~]] which calls [[https://github.com/qemu/qemu/blob/v4.2.0/target/i386/excp_helper.c#L349-L673][~handle_mmu_fault~]] (x86-specific)
- In the load/store slow path, ~load_helper~ / ~store_helper~ insert an entry in the TLB: [[https://github.com/qemu/qemu/blob/v4.2.0/accel/tcg/cputlb.c#L1682-L1691]]
+ ~[[https://github.com/qemu/qemu/blob/v4.2.0/accel/tcg/cputlb.c#L895-L912][tlb_fill]]~ (generic) calls [[https://github.com/qemu/qemu/blob/v4.2.0/target/i386/excp_helper.c#L676-L702][~x86_cpu_tlb_fill~]] which calls [[https://github.com/qemu/qemu/blob/v4.2.0/target/i386/excp_helper.c#L344-L673][~handle_mmu_fault~]] (x86-specific)
+ ~handle_mmu_fault~ first finds the physical address associated to the virtual address of the memory access while checking access rights at the same time, then calls [~tlb_set_page_with_attrs~](https://github.com/qemu/qemu/blob/v4.2.0/accel/tcg/cputlb.c#L695-L870) (generic), which:
+ finds the memory region backing the physical address: [[https://github.com/qemu/qemu/blob/v4.2.0/accel/tcg/cputlb.c#L732-L733]]
+ for an MMIO region, tags with ~TLB_MMIO~ the virtual address which will figure in the TLB entry: [[https://github.com/qemu/qemu/blob/v4.2.0/accel/tcg/cputlb.c#L782-L785]]
+ after applying some cache replacement strategy, sets the TLB entry: [[https://github.com/qemu/qemu/blob/v4.2.0/accel/tcg/cputlb.c#L867-L868]]
- So this TLB entry is filled with the ~TLB_MMIO~ flag set on the relevant address(es) field(s) (~addr_read~ or ~addr_write~ depending on the memory region properties and the MMU protections set)
- So this TLB entry is filled with the ~TLB_MMIO~ flag set on the relevant virtual address(es) field(s) (~addr_read~ or ~addr_write~ depending on the memory region properties and the MMU protections set)
+ Note that in ~load_helper~ / ~store_helper~, ~tlb_addr~ is the ~addr_read~ / ~addr_write~ field of the TLB entry (~addr_code~ is only used for instruction fetches)
- On a TLB lookup, the generated code checks flags in the relevant virtual address field of the entry (~addr_read~ or ~addr_write~) and produces a miss (that is jumps to the slow path) if any flag (eg ~TLB_MMIO~) is set: [[https://github.com/qemu/qemu/blob/v4.2.0/tcg/i386/tcg-target.inc.c#L1748-L1759]]
......
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