Commit 2cdefb9c authored by RILLING Louis's avatar RILLING Louis
Browse files

Try harder to fix links in

parent 8761a129
Pipeline #154543 failed with stages
in 5 minutes and 11 seconds
......@@ -73,7 +73,7 @@
- The TLB is initially empty.
- In the load/store slow path, ~load_helper~ / ~store_helper~ insert an
entry in the TLB: [[]]
+ [[~tlb_fill~]]( (generic) calls [~x86_cpu_tlb_fill~]( which calls [~handle_mmu_fault~]( (x86-specific)
+ [[~tlb_fill~](] (generic) calls [~x86_cpu_tlb_fill~]( which calls [~handle_mmu_fault~]( (x86-specific)
+ ~handle_mmu_fault~ first finds the physical address associated to the virtual address of the memory access while checking access rights at the same time, then calls [~tlb_set_page_with_attrs~]( (generic), which:
+ finds the memory region backing the physical address: [[]]
+ for an MMIO region, tags with ~TLB_MMIO~ the virtual address which will figure in the TLB entry: [[]]
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