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<div class="title">
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<h1><a href="./">StarPU</a></h1>
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<h2>A Unified Runtime System for Heterogeneous Multicore Architectures</h2>
</div>
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<div class="menu">
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<a href="https://team.inria.fr/storm/">STORM TEAM</a> |
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&nbsp; &nbsp; &nbsp;
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|
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<a href="#overview">Overview</a> |
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<a href="#news">News</a> |
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<a href="#contact">Contact</a> |
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<a href="people/">People</a> |
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<a href="#features">Features</a> |
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<a href="#software">Software</a> |
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<a href="#tryit">Try it!</a> |
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<a href="help/">Help</a> |
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<a href="#publications">Publications</a> |
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<a href="internships/">Jobs/Interns</a> |
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<a href="files/">Download</a> |
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<a href="market/">Market</a> |
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<a href="tutorials/">Tutorials</a> |
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<a href="https://gforge.inria.fr/plugins/mediawiki/wiki/starpu/index.php/Main_Page">Intranet</a>
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</div>
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<div class="section" id="overview">
<h3>Overview</h3>
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  <p>
<span class="important">StarPU is a task programming library for hybrid architectures</span>
<ol>
<li><b>The application provides algorithms and constraints</b>
    <ul>
    <li>CPU/GPU implementations of tasks</li>
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    <li>A graph of tasks, using either the StarPU's high level <b>GCC plugin</b> pragmas, StarPU's rich <b>C/C++ API</b>, or <b>OpenMP pragmas</b>.</li>
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    </ul>
<br>
</li>
<li><b>StarPU handles run-time concerns</b>
    <ul>
    <li>Task dependencies</li>
    <li>Optimized heterogeneous scheduling</li>
    <li>Optimized data transfers and replication between main memory and discrete memories</li>
    <li>Optimized cluster communications</li>
    </ul>
</li>
</ol>
</p>
<p>
<span class="important">Rather than handling low-level issues, <b>programmers can concentrate on algorithmic concerns!</b></span>
</p>

<p>
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<span class="note">The StarPU documentation is available in
<a href="./doc/starpu.pdf">PDF</a> and in <a href="./doc/html/">HTML</a>.</span>
Please note that these documents are up-to-date with the latest release of
StarPU.
</p>
<p>
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The latest documentation in <a href="./testing/master/doc/starpu.pdf">PDF</a>
and <a href="./testing/master/doc/html">HTML</a> is updated everyday, but covers
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the latest developments which may not be available in the latest release.
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</p>
</div>

<div class="section emphasize newslist" id="news">
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<h3>News</h3>
<p>
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March
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2019 <b>&raquo;&nbsp;</b><a href="http://gforge.inria.fr/frs/?group_id=1570"><b>The
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      second release candidate for StarPU 1.3.0 is now
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      available!</b></a> The 1.3 release brings among other
      functionalities a MPI master-slave support, a tool to replay
      execution through SimGrid, a HDF5 implementation of the
      Out-of-core, a new implementation of StarPU-MPI on top of
      NewMadeleine, implicit support for asynchronous partition
      planning, a resource management module to share processor cores
      and accelerator devices with other parallel runtime systems, ...
</p>
<p>
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February 2019 <b>&raquo;&nbsp;</b><a href="http://gforge.inria.fr/frs/?group_id=1570"><b>The
      1.2.8 release of StarPU is now available!</b></a>.
	The 1.2 release serie notably brings an out-of-core support, a MIC Xeon
	Phi support, an OpenMP runtime support, and a new internal
	communication system for MPI.
	(The release 1.2.7 is broken and should not be used)
</p>
<p>
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September 2018 <b>&raquo;&nbsp;</b><a href="http://gforge.inria.fr/frs/?group_id=1570"><b>The
      1.2.6 release of StarPU is now available!</b></a>.
      The 1.2 release serie notably brings an out-of-core support, a MIC Xeon
      Phi support, an OpenMP runtime support, and a new internal
      communication system for MPI.
</p>
<p>
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August 2018 <b>&raquo;&nbsp;</b><a href="http://gforge.inria.fr/frs/?group_id=1570"><b>The
      1.2.5 release of StarPU is now available!</b></a>.
      The 1.2 release serie notably brings an out-of-core support, a MIC Xeon
      Phi support, an OpenMP runtime support, and a new internal
      communication system for MPI.
</p>
<p>
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Avril 2018 <b>&raquo;&nbsp;</b><a href="http://gforge.inria.fr/frs/?group_id=1570"><b>The
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      1.2.4 release of StarPU is now available!</b></a>.
      The 1.2 release serie notably brings an out-of-core support, a MIC Xeon
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      Phi support, an OpenMP runtime support, and a new internal
      communication system for MPI.
</p>
<p>
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March 2018 <b>&raquo;&nbsp;</b>A <a href="https://events.prace-ri.eu/event/681/">tutorial</a>
      "Runtime systems for heterogeneous platform programming" will be
      given at the Maison de la Simulation in June 2018.
</p>
<p>
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November 2017 <b>&raquo;&nbsp;</b><a href="http://gforge.inria.fr/frs/?group_id=1570"><b>The
      1.2.3 release of StarPU is now available!</b></a>.
      This release notably brings an out-of-core support, a MIC Xeon
      Phi support, an OpenMP runtime support, and a new internal
      communication system for MPI.
</p>
<p>
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May 2017 <b>&raquo;&nbsp;</b> StarPU is part of the HPCLib project
  that aims at performing static analysis of the Inria Bordeaux
  Sud-Ouest solver stack. See
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  the <a href="https://sonarqube.bordeaux.inria.fr/sonarqube/dashboard?id=storm%3Astarpu%3Arelease%3Av1.2">StarPU
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  page</a> on the sonarqube server of INRIA.
</p>
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</div>
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<div class="section emphasizebot" style="text-align: right; font-style: italic;">
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Get the latest StarPU news by subscribing to the <a href="http://lists.gforge.inria.fr/cgi-bin/mailman/listinfo/starpu-announce">starpu-announce mailing list</a>.
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See also the full <a href="news/">news</a>.
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</div>

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<div class="section" id="video">
<h3>Video Conference</h3>
<p>
A video recording (26') of a <a href=http://www.x.org/wiki/Events/XDC2014/XDC2014ThibaultStarPU/>presentation at the XDC2014 conference</a> gives an overview of StarPU
(<a href=http://www.x.org/wiki/Events/XDC2014/XDC2014ThibaultStarPU/xdc_starpu.pdf>slides</a>):
</p>
<center>
<iframe width="420" height="315" src="https://www.youtube.com/embed/frsWSqb8UJU" frameborder="0" allowfullscreen></iframe>
</center>
</div>

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<div class="section" id="tutorial">
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<h3>Tutorial material</h3>
<p>
The latest tutorial material for StarPU is composed of two parts:
<ul>
<li><a href="http://starpu.gforge.inria.fr/tutorials/2016-06-PATC/slides/01_introducing_starpu.pdf">Introducing StarPU</a></li>
<li><a href="http://starpu.gforge.inria.fr/tutorials/2016-06-PATC/slides/02_mastering_starpu.pdf">Mastering StarPU</a></li>
</ul>
</p>
</div>

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<div class="section" id="slides">
<h3>Set of slides</h3>
<p>
A <a href="slides.pdf">set of slides</a> is also available to get an overview of
StarPU.
</p>
</div>

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<div class="section" id="contact">
<h3>Contact</h3>
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<p>For any questions regarding StarPU, please contact the StarPU developers mailing list.</p>
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<pre>
<a href="mailto:starpu-devel@lists.gforge.inria.fr?subject=StarPU">starpu-devel@lists.gforge.inria.fr</a>
</pre>
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<p>Details of the <a href="people/">StarPU team people</a> are also available.</p>
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</div>

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<div class="section" id="features">
<h3>Features</h3>
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<h4>Portability</h4>
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  <p>
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Portability is obtained by the means of a unified abstraction of the machine.
StarPU offers a unified offloadable task abstraction named <em>codelet</em>. Rather
than rewriting the entire code, programmers can encapsulate existing functions
within codelets. In case a codelet can run on heterogeneous architectures, <b>it
is possible to specify one function for each architectures</b> (e.g. one function
for CUDA and one function for CPUs). StarPU takes care of scheduling and
executing those codelets as efficiently as possible over the entire machine, include
multiple GPUs.
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One can even specify <b>several functions for each architecture</b> (new in
v1.0) as well as
<b>parallel implementations</b> (e.g. in OpenMP), and StarPU will
automatically determine which version is best for each input size (new in v0.9).
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  </p>

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<h4>Genericity</h4>
  <p>
The StarPU programming interface is very generic. For intance, various data
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structures are supported mainline (vectors, dense matrices, CSR/BCSR/COO sparse matrices, ...),
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but application-specific data structures can also be supported, provided that
the application describes how data is to be transfered (e.g. a series of
contiguous blocks). That was for instance used for hierarchically-compressed
matrices (h-matrices).
  </p>

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<h4>Data transfers</h4>
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  <p>
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To relieve programmers from the burden of explicit data transfers, a high-level
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data management library enforces memory coherency over the machine: before a
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codelet starts (e.g. on an accelerator), all its <b>data are automatically made
available on the compute resource</b>. Data are also kept on e.g. GPUs as long as
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they are needed for further tasks. When a device runs out of memory, StarPU uses
an LRU strategy to <b>evict unused data</b>. StarPU also takes care of <b>automatically
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prefetching</b> data, which thus permits to <b>overlap data transfers with computations</b>
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(including <b>GPU-GPU direct transfers</b>) to achieve the most of the architecture.
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  </p>

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<h4>Dependencies</h4>
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  <p>
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Dependencies between tasks can be given either of several ways, to provide the
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programmer with best flexibility:
  <ul>
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    <li><b>implicitly</b> from RAW, WAW, and WAR data dependencies.</li>
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    <li>explicitly through <b>tags</b> which act as rendez-vous points between
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    tasks (thus including tasks which have not been created yet),</li>
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    <li><b>explicitly</b> between pairs of tasks,</li>
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  </ul>
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  </p>
  <p>
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  These dependencies are computed in a completely decentralized way.
  </p>
  <p>
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StarPU also supports an OpenMP-like <a href="doc/html/DataManagement.html#DataReduction">reduction</a> access mode (new in v0.9).
  </p>
  <p>
It also supports a <a href="doc/html/DataManagement.html#DataCommute">commute</a> access mode to allow data access commutativity (new in v1.2).
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  </p>

<h4>Heterogeneous Scheduling</h4>
  <p>
StarPU obtains
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portable performances by efficiently (and easily) using all computing resources
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at the same time. StarPU also takes advantage of the <b>heterogeneous</b> nature of a
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machine, for instance by using scheduling strategies based on auto-tuned
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performance models. These determine the relative performance achieved
by the different processing units for the various kinds of task, and thus
permits to <b>automatically let processing units execute the tasks they are the best for</b>.
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Various strategies and variants are available. Some of them are centralized, but
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most of them are <b>completely distributed</b>. <i>dmdas</i> (a data-locality-aware MCT strategy,
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thus similar to heft but starts executing tasks before the whole task graph is
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submitted, thus allowing dynamic task submission and a decentralized scheduler,
as well as an energy optimizing extension), <i>eager</i> (dumb centralized
queue), <i>lws</i> (decentralized locality-aware work-stealing), ...
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The overhead per task is typically around the order of
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magnitude of a microsecond. Tasks should thus be a few orders of magnitude
bigger, such as 100 microseconds or 1 millisecond, to make the overhead
negligible.
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  </p>

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<h4>Clusters</h4>
  <p>
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To deal with clusters, StarPU can nicely integrate with <a
	href="doc/html/MPISupport.html">MPI</a>, through explicit or implicit
support, according to the application's preference.

    <ul>
        <li>Explicit network communication requests can be emitted, which will
then be <b>automatically combined and overlapped</b> with the intra-node data
transfers and computation,
        <li>The application can also just provide the whole task graph, a
data distribution over MPI nodes, and StarPU will automatically determine which
MPI node should execute which task, and <b>automatically generate all required
MPI communications</b> accordingly (new in v0.9). We have gotten excellent
scaling on a 256-node cluster with GPUs, we have not yet had the opportunity
to test on a yet larger cluster. We have however measured that with naive task
submission, it should scale to a thousand nodes, and with pruning-tuned task
submission, it should scale to about a <b>million nodes</b>.
        <li>Starting with v1.3, the application can also just provide the
whole task graph, and let StarPU decide the data distribution and task
distribution, thanks to a master-slave mechanism. This will however by nature
have a more limited scalability than the fully distributed paradigm mentioned
above.
    </ul>
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  </p>

<h4>Out of core</h4>
  <p>
When memory is not big enough for the working set, one may have to resort to
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using disks. StarPU makes this seamless thanks to its <a href="doc/html/OutOfCore.html">out of core support</a> (new in v1.2).
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StarPU will <b>automatically evict</b> data from the main memory in advance, and
<b>prefetch back</b> required data before it is needed for tasks.
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  </p>

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<h4>Extensions to the C Language</h4>
<p>
  StarPU comes with a GCC plug-in
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  that <a href="doc/html/cExtensions.html">extends the C programming
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  language</a> with pragmas and attributes that make it easy
  to <b>annotate a sequential C program to turn it into a parallel
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  StarPU program</b> (new in v1.0).
</p>

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<h4>OpenMP 4 -compatible interface</h4>
<p>
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  <a href=http://kstar.gforge.inria.fr/>K'Star</a> provides an OpenMP
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  4 -compatible interface on top of StarPU. This allows to just rebuild OpenMP
  applications with the K'Star source-to-source compiler, then build it with the
  usual compiler, and the result will use the StarPU runtime.
</p>
<p>
  K'Star also provides some extensions to the OpenMP 4 standard, to let the
  StarPU runtime perform online optimizations.
</p>

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<h4>OpenCL-compatible interface</h4>
<p>
  StarPU provides an <a href="doc/html/SOCLOpenclExtensions.html">OpenCL-compatible interface, SOCL</a>
  which allows to simply run OpenCL applications on top of StarPU (new in v1.0).
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</p>

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<h4>Simulation support</h4>
<p>
  StarPU can very accurately simulate an application execution
  and measure the resulting performance thanks to using the
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  <a href="http://simgrid.gforge.inria.fr">SimGrid simulator</a> (new in v1.1).  This allows
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  to quickly experiment with various scheduling heuristics, various application
  algorithms, and even various platforms (available GPUs and CPUs, available
  bandwidth)!
</p>

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<h4>All in all</h4>
  <p>
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All that means that, with the help
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of <a href="doc/html/cExtensions.html">StarPU's extensions to the C
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language</a>, the following sequential source code of a tiled version of
the classical Cholesky factorization algorithm using BLAS is also valid
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StarPU code, possibly running on all the CPUs and GPUs, and given a data
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distribution over MPI nodes, it is even a distributed version!
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  </p>

  <tt><pre>
for (k = 0; k < tiles; k++) {
  potrf(A[k,k])
  for (m = k+1; m < tiles; m++)
    trsm(A[k,k], A[m,k])
  for (m = k+1; m < tiles; m++)
    syrk(A[m,k], A[m, m])
  for (m = k+1, m < tiles; m++)
    for (n = k+1, n < m; n++)
      gemm(A[m,k], A[n,k], A[m,n])
}</pre></tt>
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<h4>Supported Architectures</h4>
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<ul>
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<li>SMP/Multicore Processors (x86, PPC, ARM, ... all Debian architecture have been tested) </li>
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<li>NVIDIA GPUs (e.g. heterogeneous multi-GPU), with pipelined and concurrent kernel execution support (new in v1.2) and GPU-GPU direct transfers (new in v1.1)</li>
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<li>OpenCL devices</li>
<li>Cell Processors (experimental)</li>
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<li>Intel SCC (experimental, new in v1.2)</li>
<li>Intel MIC / Xeon Phi (new in v1.2)</li>
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</ul>
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<h4>Supported Operating Systems</h4>
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<ul>
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<li>GNU/Linux</li>
<li>Mac OS X</li>
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<li>Windows</li>
</ul>

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<h4>Stability</h4>
<p>
StarPU is checked every night with
<ul>
<li>Valgrind / Helgrind</li>
<li>gcc' Address/Leak/Thread/Undefined Sanitizers</li>
<li>cppcheck</li>
<li>Coverity</li>
</ul>
</p>

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<h4>Performance analysis tools</h4>
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  <p>
In order to understand the performance obtained by StarPU, it is helpful to
visualize the actual behaviour of the applications running on complex
heterogeneous multicore architectures.  StarPU therefore makes it possible to
generate Pajé traces that can be visualized thanks to the <a
href="http://vite.gforge.inria.fr/"><b>ViTE</b> (Visual Trace Explorer) open
source tool.</a>
  </p>

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<p>
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<b>Example:</b> LU decomposition on 3 CPU cores and a GPU using a very simple
greedy scheduling strategy. The green (resp. red) sections indicate when the
corresponding processing unit is busy (resp. idle). The number of ready tasks
is displayed in the curve on top: it appears that with this scheduling policy,
the algorithm suffers a certain lack of parallelism. <b>Measured speed: 175.32
GFlop/s</b>
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<center><a href="./images/greedy-lu-16k-fx5800.png"> <img src="./images/greedy-lu-16k-fx5800.png" alt="LU decomposition (greedy)" width="75%"></a></center>
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</p>

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<p>
This second trace depicts the behaviour of the same application using a
scheduling strategy trying to minimize load imbalance thanks to auto-tuned
performance models and to keep data locality as high as possible. In this
example, the Pajé trace clearly shows that this scheduling strategy outperforms
the previous one in terms of processor usage. <b>Measured speed: 239.60
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GFlop/s</b>
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<center><a href="./images/dmda-lu-16k-fx5800.png"><img src="./images/dmda-lu-16k-fx5800.png" alt="LU decomposition (dmda)" width="75%"></a></center>
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</p>

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<p>
<a href="http://www.hlrs.de/temanejo">Temanejo</a> can be used to debug the task
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graph, as shown below (new in v1.1).
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</p>

<center>
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<a href="images/temanejo.png"><img src="images/temanejo.png" width="50%"/></a>
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</center>

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</div>

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<div class="section" id="software">
<h3>Software using StarPU</h3>

<p>
Some software is known for being able to use StarPU to tackle heterogeneous
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architectures, here is a non-exhaustive list (feel free to ask to be added to the
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list!):
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</p>

<ul>
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	<li>AL4SAN, dense linear algebra library</li>
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	<li><a href="https://project.inria.fr/chameleon/">Chameleon</a>, dense linear algebra library</li>
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	<li><a href="http://exa2pro.eu">Exa2pro</a>, Enhancing Programmability and boosting Performance Portability for Exascale Computing Systems</li>
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	<li><a href="http://github.com/ecrc/exageostat">ExaGeoStat</a>, Machine learning framework for Climate/Weather prediction applications</li>
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	<li><a href="https://hal.inria.fr/hal-01507613">FLUSEPA</a>, Navier-Stokes Solver for Unsteady Problems with Bodies in Relative Motion</li>
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	<li><a href="http://github.com/ecrc/hicma">HiCMA</a>, Low-rank general linear algebra library</li>
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	<li>hmat, hierarchical matrix C/C++ library</li>
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        <li><a href=http://kstar.gforge.inria.fr/>K'Star</a>, OpenMP 4 - compatible interface on top of StarPU.</li>
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	<li><a href="http://github.com/ecrc/ksvd">KSVD</a>, dense SVD on distributed-memory manycore systems</li>
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	<li><a href="http://icl.cs.utk.edu/magma/">MAGMA</a>, dense linear algebra library, starting from version 1.1</li>
	<li><a href="https://gitlab.inria.fr/solverstack/maphys">MaPHyS</a>, Massively Parallel Hybrid Solver</li>
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	<li><a href="http://github.com/ecrc/moao">MOAO</a>, HPC framework for computational astronomy, servicing the European Extremely Large Telescope and the Japanese Subaru Telescope</li>
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	<li><a href="http://pastix.gforge.inria.fr/">PaStiX</a>, sparse linear algebra library, starting from version 5.2.1</li>
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	<li>PEPPHER, Performance Portability and Programmability for Heterogeneous Many-core Architectures</li>
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	<li><a href="http://github.com/ecrc/qdwh">QDWH</a>, QR-based Dynamically Weighted Halley</li>
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	<li><a href="http://buttari.perso.enseeiht.fr/qr_mumps/">qr_mumps</a>, sparse linear algebra library</li>
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	<li><a href="http://scalfmm-public.gforge.inria.fr/doc/">ScalFMM</a>, N-body interaction simulation using the Fast Multipole Method. </li>
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	<li><a href="https://tel.archives-ouvertes.fr/tel-01410049/">SCHNAPS</a>, Solver for Conservative Hypebolic Non-linear systems Applied to PlasmaS. </li>
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	<li><a href="https://hal.archives-ouvertes.fr/hal-01086246">SignalPU</a>, a Dataflow-Graph-specific programming model. </li>
	<li><a href="http://www.ida.liu.se/~chrke/skepu/">SkePU</a>, a skeleton programming framework.</li>
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	<li><a href="http://github.com/ecrc/stars-h">STARS-H</a>, HPC low-rank matrix market</li>
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	<li><a href="http://www.xcalablemp.org/">XcalableMP</a>, Directive-based language eXtension for Scalable and performance-aware Parallel Programming</li>
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</ul>

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<p>
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You can find <a href="#PublicationsOnApplications">below</a> the list of publications related to applications using StarPU.
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</p>

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</div>

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<div class="section" id="tryit">
<h3>Give it a try!</h3>
<p>
You can easily try the performance on the Cholesky factorization for
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instance. Make sure to have the pkg-config and
<a href="http://www.open-mpi.org/projects/hwloc/">hwloc</a>
software installed for
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proper CPU control and BLAS kernels for your computation units and configured in
your environment (e.g. MKL for CPUs and CUBLAS for GPUs).
</p>
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<tt><pre>
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$ wget http://starpu.gforge.inria.fr/files/starpu-someversion.tar.gz
$ tar xf starpu-someversion.tar.gz
$ cd starpu-someversion
$ ./configure
$ make -j 12
$ STARPU_SCHED=dmdas ./examples/cholesky/cholesky_implicit -size $((960*40)) -nblocks 40
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$ STARPU_SCHED=dmdas mpirun -np 4 -machinefile mymachines ./mpi/examples/matrix_decomposition/mpi_cholesky_distributed -size $((960*40*4)) -nblocks $((40*4))</pre></tt>
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<p>Note that the dmdas scheduler uses performance models, and thus needs
calibration execution before exhibiting optimized performance (until the "model
something is not calibrated enough" messages go away).</p>

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<p>To get a glimpse at what happened, you can get an execution trace by
installing
<a href="http://savannah.nongnu.org/projects/fkt">FxT</a>
and <a href="http://vite.gforge.inria.fr/">ViTE</a>, and enabling traces:
</p>

<tt><pre>
$ ./configure --with-fxt
$ make -j 12
$ STARPU_SCHED=dmdas ./examples/cholesky/cholesky_implicit -size $((960*40)) -nblocks 40
$ ./tools/starpu_fxt_tool -i /tmp/prof_file_${USER}_0
$ vite paje.trace
</pre></tt>

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<p>
Starting with StarPU 1.1, it is also possible to reproduce the performance that
we show in our articles on our machines, by installing simgrid, and then using
the simulation mode of StarPU using the performance models of our machines:
</p>
  <tt><pre>
$ ./configure --enable-simgrid
$ make -j 12
$ STARPU_PERF_MODEL_DIR=$PWD/tools/perfmodels/sampling STARPU_HOSTNAME=mirage STARPU_SCHED=dmdas ./examples/cholesky/cholesky_implicit -size $((960*40)) -nblocks 40
# size	ms	GFlops
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38400	9915	1903.7</pre></tt>
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<p>(MPI simulation is not supported yet)</p>

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<div class="section" id="publications">
<h3>Publications</h3>
<p>
All StarPU related publications are also
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listed <a href="./publications">here</a>
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with the corresponding Bibtex entries.
</p>

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<p>
A good overview is available in
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the following <a href="http://hal.archives-ouvertes.fr/inria-00467677">Research Report</a>.
</p>

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<p>
If you need to cite StarPU, please
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reference <a href="publications/Year/2011.html#AugThiNamWac11CCPE">[StarPU: A Unified Platform
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    for Task Scheduling on Heterogeneous Multicore Architectures]</a>
for a general presentation. Other sub-sections below will give you
references for more specific aspects of StarPU.
</p>

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<h4>General Presentations</h4> 
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<a name="PublicationsGeneralPresentations"></a>
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<ol>
<li>
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<a name="thibault:tel-01959127"></a>Samuel Thibault<br/>
<strong>On Runtime Systems for Task-based Programming on Heterogeneous Platforms</strong><br/>
Habilitation à diriger des recherches, Université de Bordeaux, December 2018<br/>
[<a href="https://hal.inria.fr/tel-01959127">WWW</a>]
[<a href="https://hal.inria.fr/tel-01959127/file/hdr.pdf">PDF</a>]
</li>
<li>
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<a name="Aug11Thesis"></a>Cédric Augonnet<br/>
<strong>Scheduling Tasks over Multicore machines enhanced with Accelerators: a Runtime System's Perspective</strong><br/>
PhD thesis, Université Bordeaux 1, 351 cours de la Libération --- 33405 TALENCE cedex, December 2011<br/>
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[<a href="http://tel.archives-ouvertes.fr/tel-00777154">WWW</a>]
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[<a href="http://tel.archives-ouvertes.fr/tel-00777154/document">PDF</a>]
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</li>
<li>
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<a name="AugThiNamWac11CCPE"></a>Cédric Augonnet, Samuel Thibault, Raymond Namyst,  and Pierre-André Wacrenier<br/>
<strong>StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures</strong><br/>
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<em>CCPE - Concurrency and Computation: Practice and Experience, Special Issue: Euro-Par 2009</em>, 23:187-198, February 2011<br/>
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[<a href="http://hal.inria.fr/inria-00550877">WWW</a>]
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[<a href="http://hal.inria.fr/inria-00550877/document">PDF</a>]
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[doi:<a href="http://dx.doi.org/10.1002/cpe.1631">10.1002/cpe.1631</a>]
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</li>
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<li>
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<a name="AugThiNamWac10RR7240"></a>Cédric Augonnet, Samuel Thibault,  and Raymond Namyst<br/>
<strong>StarPU: a Runtime System for Scheduling Tasks over Accelerator-Based Multicore Machines</strong><br/>
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Research Report RR-7240, INRIA, March 2010<br/>
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[<a href="http://hal.inria.fr/inria-00467677">WWW</a>]
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[<a href="http://hal.inria.fr/inria-00467677/document">PDF</a>]
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</li>
<li>
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<a name="Aug09Renpar19"></a>Cédric Augonnet<br/>
<strong>StarPU: un support exécutif unifié pour les architectures multicoeurs hétérogènes</strong><br/>
In <em>19èmes Rencontres Francophones du Parallélisme</em>, Toulouse / France, September 2009<br/>
Note: Best Paper Award<br/>
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[<a href="http://hal.inria.fr/inria-00411581">WWW</a>]
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[<a href="http://hal.inria.fr/inria-00411581/document">PDF</a>]
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</li>
<li>
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<a name="AugThiNamWac09Europar"></a>Cédric Augonnet, Samuel Thibault, Raymond Namyst,  and Pierre-André Wacrenier<br/>
<strong>StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures</strong><br/>
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In <em>Euro-Par - 15th International Conference on Parallel Processing</em>, volume 5704 of <em>Lecture Notes in Computer Science</em>, Delft, The Netherlands, pages 863-874, August 2009<br/>
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Springer<br/>
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[<a href="http://hal.inria.fr/inria-00384363">WWW</a>]
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[<a href="http://hal.inria.fr/inria-00384363/document">PDF</a>]
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[doi:<a href="http://dx.doi.org/10.1007/978-3-642-03869-3_80">10.1007/978-3-642-03869-3_80</a>]
</li>
<li>
<a name="AugNam08HPPC"></a>Cédric Augonnet and Raymond Namyst<br/>
<strong>A unified runtime system for heterogeneous multicore architectures</strong><br/>
In <em>Proceedings of the International Euro-Par Workshops 2008, HPPC'08</em>, volume 5415 of <em>Lecture Notes in Computer Science</em>, Las Palmas de Gran Canaria, Spain, pages 174-183, August 2008<br/>
Springer<br/>
<strong>ISBN:</strong> 978-3-642-00954-9<br/>
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[<a href="http://hal.inria.fr/inria-00326917">WWW</a>]
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[<a href="http://hal.inria.fr/inria-00326917/document">PDF</a>]
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[doi:<a href="http://dx.doi.org/10.1007/978-3-642-00955-6_22">10.1007/978-3-642-00955-6_22</a>]
</li>
<li>
<a name="Aug08Master"></a>Cédric Augonnet<br/>
<strong>Vers des supports d'exécution capables d'exploiter les machines multicoeurs hétérogènes</strong><br/>
Mémoire de DEA, Université Bordeaux 1, June 2008<br/>
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[<a href="http://hal.inria.fr/inria-00289361">WWW</a>]
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[<a href="http://hal.inria.fr/inria-00289361/document">PDF</a>]
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</li>
</ol>
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<h4>On Composability</h4> 
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<a name="PublicationsOnComposability"></a>
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<ol>
<li>
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<a name="hugo:tel-01162975"></a>Andra-Ecaterina Hugo<br/>
<strong>Composability of parallel codes on heterogeneous architectures</strong><br/>
Theses, Université de Bordeaux, December 2014<br/>
[<a href="https://tel.archives-ouvertes.fr/tel-01162975">WWW</a>]
[<a href="https://tel.archives-ouvertes.fr/tel-01162975/file/HUGO_ANDRA_2014.pdf">PDF</a>]
</li>
<li>
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<a name="AH13Renpar"></a>Andra Hugo<br/>
<strong>Le problème de la composition parallèle : une approche supervisée</strong><br/>
In <em>21èmes Rencontres Francophones du Parallélisme (RenPar'21)</em>, Grenoble, France, January 2013<br/>
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[<a href="http://hal.inria.fr/hal-00773610">WWW</a>]
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[<a href="http://hal.inria.fr/hal-00773610/document">PDF</a>]
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</li>
<li>
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<a name="hugo:hal-00824514"></a>Andra Hugo, Abdou Guermouche, Raymond Namyst,  and Pierre-André Wacrenier<br/>
<strong>Composing multiple StarPU applications over heterogeneous machines: a supervised approach</strong><br/>
In <em>Third International Workshop on Accelerators and Hybrid Exascale Systems</em>, Boston, USA, May 2013<br/>
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[<a href="http://hal.inria.fr/hal-00824514">WWW</a>]
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[<a href="http://hal.inria.fr/hal-00824514/document">PDF</a>]
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</li>
<li>
<a name="AH11Master"></a>Andra Hugo<br/>
<strong>Composabilité de codes parallèles sur architectures hétérogènes</strong><br/>
Mémoire de Master, Université Bordeaux 1, June 2011<br/>
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[<a href="http://hal.inria.fr/inria-00619654/en/">WWW</a>]
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[<a href="http://hal.inria.fr/inria-00619654/document">PDF</a>]
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</li>
</ol>
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<h4>On Parallel Tasks</h4> 
<a name="PublicationsOnParallelTasks"></a>
<ol>
<li>
<a name="cojean:tel-01816341"></a>Terry Cojean<br/>
<strong>Programmation of heterogeneous architectures using moldable tasks</strong><br/>
Theses, Université de Bordeaux, March 2018<br/>
[<a href="https://tel.archives-ouvertes.fr/tel-01816341">WWW</a>]
[<a href="https://tel.archives-ouvertes.fr/tel-01816341/file/COJEAN_TERRY_2018.pdf">PDF</a>]
</li>
</ol>
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<h4>On Scheduling</h4> 
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<a name="PublicationsOnScheduling"></a>
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<ol>
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<li>
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<a name="garciapinto:hal-01616632"></a>Vinicius Garcia Pinto, Lucas Mello Schnorr, Luka Stanisic, Arnaud Legrand, Samuel Thibault,  and Vincent Danjean<br/>
<strong>A Visual Performance Analysis Framework for Task-based Parallel Applications running on Hybrid Clusters</strong><br/>
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<em>CCPE - Concurrency and Computation: Practice and Experience</em>, 30, April 2018<br/>
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[<a href="https://hal.inria.fr/hal-01616632">WWW</a>]
[<a href="https://hal.inria.fr/hal-01616632/file/CCPE_article_submitted_2018_02_06.pdf">PDF</a>]
[doi:<a href="http://dx.doi.org/10.1002/cpe.4472">10.1002/cpe.4472</a>]
</li>
<li>
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<a name="pinto:hal-01842038"></a>Vinicius Garcia Pinto, Lucas Mello Schnorr, Arnaud Legrand, Samuel Thibault, Luka Stanisic,  and Vincent Danjean<br/>
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<strong>Detecç ao de Anomalias de Desempenho em Aplicaç oes de Alto Desempenho baseadas em Tarefas em Clusters Hìbridos</strong><br/>
In <em>WPerformance - 17º Workshop em Desempenho de Sistemas Computacionais e de Comunicaç ao</em>, Natal, Brazil, July 2018<br/>
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[<a href="https://hal.inria.fr/hal-01842038">WWW</a>]
[<a href="https://hal.inria.fr/hal-01842038/file/181587_1.pdf">PDF</a>]
</li>
<li>
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<a name="kumar:tel-01538516"></a>Suraj Kumar<br/>
<strong>Scheduling of Dense Linear Algebra Kernels on Heterogeneous Resources</strong><br/>
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PhD thesis, Université de Bordeaux, April 2017<br/>
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[<a href="https://tel.archives-ouvertes.fr/tel-01538516">WWW</a>]
[<a href="https://tel.archives-ouvertes.fr/tel-01538516/file/KUMAR_SURAL_2017.pdf">PDF</a>]
</li>
<li>
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<a name="beaumont:hal-01386174"></a>O. Beaumont, L. Eyraud-Dubois,  and S. Kumar<br/>
<strong>Approximation Proofs of a Fast and Efficient List Scheduling Algorithm for Task-Based Runtime Systems on Multicores and GPUs</strong><br/>
In <em>2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS)</em>, pages 768-777, May 2017<br/>
[<a href="https://hal.inria.fr/hal-01386174">WWW</a>]
[<a href="https://hal.inria.fr/hal-01386174/file/heteroPrioApproxProofsRR.pdf">PDF</a>]
[doi:<a href="http://dx.doi.org/10.1109/IPDPS.2017.71">10.1109/IPDPS.2017.71</a>]
</li>
<li>
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<a name="agullo:hal-01223573"></a>Emmanuel Agullo, Olivier Beaumont, Lionel Eyraud-Dubois,  and Suraj Kumar<br/>
<strong>Are Static Schedules so Bad ? A Case Study on Cholesky Factorization</strong><br/>
In <em>IPDPS'16</em>, Proceedings of the 30th IEEE International Parallel & Distributed Processing Symposium, IPDPS'16, Chicago, IL, United States, May 2016<br/>
IEEE<br/>
[<a href="https://hal.inria.fr/hal-01223573">WWW</a>]
[<a href="https://hal.inria.fr/hal-01223573/file/heteroprioCameraReady-ieeeCompatiable.pdf">PDF</a>]
</li>
<li>
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<a name="beaumont:hal-01361992"></a>Olivier Beaumont, Terry Cojean, Lionel Eyraud-Dubois, Abdou Guermouche,  and Suraj Kumar<br/>
<strong>Scheduling of Linear Algebra Kernels on Multiple Heterogeneous Resources</strong><br/>
In <em>International Conference on High Performance Computing, Data, and Analytics (HiPC)</em>, Hyderabad, India, December 2016<br/>
[<a href="https://hal.inria.fr/hal-01361992">WWW</a>]
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[<a href="https://hal.inria.fr/hal-01361992v2/document">PDF</a>]
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</li>
<li>
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<a name="cojean:hal-01181135"></a>Terry Cojean, Abdou Guermouche, Andra Hugo, Raymond Namyst,  and Pierre-André Wacrenier<br/>
<strong>Resource aggregation for task-based Cholesky Factorization on top of heterogeneous machines</strong><br/>
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In <em>HeteroPar'2016 workshop of Euro-Par</em>, Grenoble, France, August 2016<br/>
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[<a href="https://hal.inria.fr/hal-01181135">WWW</a>]
[<a href="https://hal.inria.fr/hal-01181135/file/papier%20%281%29.pdf">PDF</a>]
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</li>
<li>
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<a name="garciapinto:hal-01353962"></a>Vinicius Garcia Pinto, Luka Stanisic, Arnaud Legrand, Lucas Mello Schnorr, Samuel Thibault,  and Vincent Danjean<br/>
<strong>Analyzing Dynamic Task-Based Applications on Hybrid Platforms: An Agile Scripting Approach</strong><br/>
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In <em>VPA - 3rd Workshop on Visual Performance Analysis</em>, Salt Lake City, United States, November 2016<br/>
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Note: Held in conjunction with SC16<br/>
[<a href="https://hal.inria.fr/hal-01353962">WWW</a>]
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[<a href="https://hal.inria.fr/hal-01353962v2/document">PDF</a>]
[doi:<a href="http://dx.doi.org/10.1109/VPA.2016.008">10.1109/VPA.2016.008</a>]
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</li>
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<li>
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<a name="JaBlHU2016a"></a>Johan Janzén, David Black-Schaffer,  and Andra Hugo<br/>
<strong>Partitioning GPUs for Improved Scalability</strong><br/>
In <em>IEEE 28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)</em>, October 2016<br/>
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[<a href="http://ieeexplore.ieee.org/abstract/document/7789322/">WWW</a>]
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[doi:<a href="http://dx.doi.org/10.1109/SBAC-PAD.2016.14">10.1109/SBAC-PAD.2016.14</a>]
</li>
<li>
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<a name="cojean:hal-01409965"></a>Terry Cojean, Abdou Guermouche, Andra Hugo, Raymond Namyst,  and Pierre-André Wacrenier<br/>
<strong>Resource aggregation for task-based Cholesky Factorization on top of modern architectures</strong><br/>
Note: This paper is submitted for review to the Parallel Computing special issue for HCW and HeteroPar 16 workshops, November 2016<br/>
[<a href="https://hal.inria.fr/hal-01409965">WWW</a>]
[<a href="https://hal.inria.fr/hal-01409965/file/submission.pdf">PDF</a>]
</li>
<li>
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<a name="agullo:hal-01120507"></a>Emmanuel Agullo, Olivier Beaumont, Lionel Eyraud-Dubois, Julien Herrmann, Suraj Kumar, Loris Marchal,  and Samuel Thibault<br/>
<strong>Bridging the Gap between Performance and Bounds of Cholesky Factorization on Heterogeneous Platforms</strong><br/>
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In <em>HCW'2015 - Heterogeneity in Computing Workshop of IPDPS</em>, Hyderabad, India, May 2015<br/>
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[<a href="https://hal.inria.fr/hal-01120507">WWW</a>]
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[<a href="https://hal.inria.fr/hal-01120507/document">PDF</a>]
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[doi:<a href="http://dx.doi.org/10.1109/IPDPSW.2015.35">10.1109/IPDPSW.2015.35</a>]
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<a name="sergent:hal-00978364"></a>Marc Sergent and Simon Archipoff<br/>
<strong>Modulariser les ordonnanceurs de tâches : une approche structurelle</strong><br/>
In <em>Compas'2014</em>, Neuchâtel, Suisse, April 2014<br/>
741 742
[<a href="http://hal.inria.fr/hal-00978364">WWW</a>]
[<a href="http://hal.inria.fr/hal-00978364/PDF/ordonnanceurs_modulaires.pdf">PDF</a>]
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<a name="AugCleThiNam10ICPADS"></a>Cédric Augonnet, Jérôme Clet-Ortega, Samuel Thibault,  and Raymond Namyst<br/>
<strong>Data-Aware Task Scheduling on Multi-Accelerator based Platforms</strong><br/>
In <em>The 16th International Conference on Parallel and Distributed Systems (ICPADS)</em>, Shanghai, China, December 2010<br/>
[<a href="http://hal.inria.fr/inria-00523937">WWW</a>]
[<a href="http://hal.inria.fr/inria-00523937/document">PDF</a>]
[doi:<a href="http://dx.doi.org/10.1109/ICPADS.2010.129">10.1109/ICPADS.2010.129</a>]
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<h4>On The C Extensions</h4> 
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<a name="LC13Report"></a>Ludovic Courtès<br/>
<strong>C Language Extensions for Hybrid CPU/GPU Programming with StarPU</strong><br/>
Research Report RR-8278, INRIA, April 2013<br/>
760 761
[<a href="http://hal.inria.fr/hal-00807033">WWW</a>]
[<a href="http://hal.inria.fr/hal-00807033/PDF/RR-8278.pdf">PDF</a>]
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</ol>
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<h4>On OpenMP Support on top of StarPU</h4> 
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<a name="PublicationsOnOpenMPSupportontopofStarPU"></a>
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<a name="agullo:hal-01517153"></a>Emmanuel Agullo, Olivier Aumage, Berenger Bramas, Olivier Coulaud,  and Samuel Pitoiset<br/>
<strong>Bridging the gap between OpenMP and task-based runtime systems for the fast multipole method</strong><br/>
<em>IEEE Transactions on Parallel and Distributed Systems</em>, April 2017<br/>
[<a href="https://hal.inria.fr/hal-01517153">WWW</a>]
[<a href="https://hal.inria.fr/hal-01517153/file/tpds_kstar_scalfmm_print.pdf">PDF</a>]
[doi:<a href="http://dx.doi.org/10.1109/TPDS.2017.2697857">10.1109/TPDS.2017.2697857</a>]
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<a name="agullo:hal-01372022"></a>Emmanuel Agullo, Olivier Aumage, Berenger Bramas, Olivier Coulaud,  and Samuel Pitoiset<br/>
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<strong>Bridging the gap between OpenMP 4.0 and native runtime systems for the fast multipole method</strong><br/>
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Research Report RR-8953, Inria, March 2016<br/>
[<a href="https://hal.inria.fr/hal-01372022">WWW</a>]
[<a href="https://hal.inria.fr/hal-01372022/file/RR-8953.pdf">PDF</a>]
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<a name="virouleau:hal-01081974"></a>Philippe Virouleau, Pierrick Brunet, François Broquedis, Nathalie Furmento, Samuel Thibault, Olivier Aumage,  and Thierry Gautier<br/>
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<strong>Evaluation of OpenMP Dependent Tasks with the KASTORS Benchmark Suite</strong><br/>
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In <em>IWOMP2014 - 10th International Workshop on OpenMP</em>, 10th International Workshop on OpenMP, IWOMP2014, Salvador, Brazil, France, pages 16 - 29, September 2014<br/>
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Springer<br/>
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[<a href="https://hal.inria.fr/hal-01081974">WWW</a>]
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[<a href="https://hal.inria.fr/hal-01081974/document">PDF</a>]
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[doi:<a href="http://dx.doi.org/10.1007/978-3-319-11454-5_2">10.1007/978-3-319-11454-5_2</a>]
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<h4>On MPI Support</h4> 
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<a name="PublicationsOnMPISupport"></a>
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<a name="agullo:hal-01618526"></a>Emmanuel Agullo, Olivier Aumage, Mathieu Faverge, Nathalie Furmento, Florent Pruvost, Marc Sergent,  and Samuel Thibault<br/>
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<strong>Achieving High Performance on Supercomputers with a Sequential Task-based Programming Model</strong><br/>
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<em>TPDS - IEEE Transactions on Parallel and Distributed Systems</em>, December 2017<br/>
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[<a href="https://hal.inria.fr/hal-01618526">WWW</a>]
[<a href="https://hal.inria.fr/hal-01618526/file/tpds14.pdf">PDF</a>]
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[doi:<a href="http://dx.doi.org/10.1109/TPDS.2017.2766064">10.1109/TPDS.2017.2766064</a>]
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<a name="sergent:tel-01483666"></a>Marc Sergent<br/>
<strong>Scalability of a task-based runtime system for dense linear algebra applications</strong><br/>
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PhD thesis, Université de Bordeaux, December 2016<br/>
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[<a href="https://tel.archives-ouvertes.fr/tel-01483666">WWW</a>]
[<a href="https://tel.archives-ouvertes.fr/tel-01483666/file/SERGENT_MARC_2016.pdf">PDF</a>]
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<a name="agullo:hal-01283949"></a>Emmanuel Agullo, Olivier Aumage, Mathieu Faverge, Nathalie Furmento, Florent Pruvost, Marc Sergent,  and Samuel Thibault<br/>
<strong>Harnessing clusters of hybrid nodes with a sequential task-based programming model</strong><br/>
In <em>8th International Workshop on Parallel Matrix Algorithms and Applications</em>, July 2014<br/>
[<a href="https://hal.inria.fr/hal-01283949">WWW</a>]
[<a href="https://hal.inria.fr/hal-01283949/file/pmaa14.pdf">PDF</a>]
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<a name="augonnet:hal-00992208"></a>Cédric Augonnet, Olivier Aumage, Nathalie Furmento, Samuel Thibault,  and Raymond Namyst<br/>
<strong>StarPU-MPI: Task Programming over Clusters of Machines Enhanced with Accelerators</strong><br/>
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Research Report RR-8538, INRIA, May 2014<br/>
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[<a href="http://hal.inria.fr/hal-00992208">WWW</a>]
[<a href="http://hal.inria.fr/hal-00992208/PDF/RR-8538.pdf">PDF</a>]
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<a name="AugAumFurNamThi2012EuroMPI"></a>Cédric Augonnet, Olivier Aumage, Nathalie Furmento, Raymond Namyst,  and Samuel Thibault<br/>
<strong>StarPU-MPI: Task Programming over Clusters of Machines Enhanced with Accelerators</strong><br/>
In Siegfried Benkner Jesper Larsson Träff and Jack Dongarra, editors, <em>EuroMPI 2012</em>, volume 7490 of <em>LNCS</em>, September 2012<br/>
Springer<br/>
Note: Poster Session<br/>
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[<a href="http://hal.inria.fr/hal-00725477">WWW</a>]
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<h4>On Memory Control</h4> 
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<a name="chevalier:hal-01718280"></a>Arthur Chevalier<br/>
<strong>Critical resources management and scheduling under StarPU</strong><br/>
Master's thesis, Université de Bordeaux, September 2017<br/>
[<a href="https://hal.inria.fr/hal-01718280">WWW</a>]
[<a href="https://hal.inria.fr/hal-01718280/file/Memoire.pdf">PDF</a>]
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<a name="sergent:hal-01284004"></a>Marc Sergent, David Goudin, Samuel Thibault,  and Olivier Aumage<br/>
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<strong>Controlling the Memory Subscription of Distributed Applications with a Task-Based Runtime System</strong><br/>
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In <em>HIPS - 21st International Workshop on High-Level Parallel Programming Models and Supportive Environments</em>, Chicago, United States, May 2016<br/>
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[<a href="https://hal.inria.fr/hal-01284004">WWW</a>]
[<a href="https://hal.inria.fr/hal-01284004/file/PID4127657.pdf">PDF</a>]
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[doi:<a href="http://dx.doi.org/10.1109/IPDPSW.2016.105">10.1109/IPDPSW.2016.105</a>]
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<h4>On Performance Model Tuning</h4> 
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<a name="agullo:hal-01474556"></a>Emmanuel Agullo, Bérenger Bramas, Olivier Coulaud, Luka Stanisic,  and Samuel Thibault<br/>
<strong>Modeling Irregular Kernels of Task-based codes: Illustration with the Fast Multipole Method</strong><br/>
Research Report RR-9036, INRIA Bordeaux, February 2017<br/>
[<a href="https://hal.inria.fr/hal-01474556">WWW</a>]
[<a href="https://hal.inria.fr/hal-01474556/file/rapport.pdf">PDF</a>]
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<a name="AugThiNam09HPPC"></a>Cédric Augonnet, Samuel Thibault,  and Raymond Namyst<br/>
<strong>Automatic Calibration of Performance Models on Heterogeneous Multicore Architectures</strong><br/>
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In <em>HPPC - Proceedings of the International Euro-Par Workshops, Highly Parallel Processing on a Chip</em>, volume 6043 of <em>Lecture Notes in Computer Science</em>, Delft, The Netherlands, pages 56-65, August 2009<br/>
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Springer<br/>
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[<a href="http://hal.inria.fr/inria-00421333">WWW</a>]
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[<a href="http://hal.inria.fr/inria-00421333/document">PDF</a>]
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[doi:<a href="http://dx.doi.org/10.1007/978-3-642-14122-5_9">10.1007/978-3-642-14122-5_9</a>]
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873
<h4>On The Simulation Support through SimGrid</h4> 
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<a name="stanisic:hal-01147997"></a>Luka Stanisic, Samuel Thibault, Arnaud Legrand, Brice Videau,  and Jean-François Méhaut<br/>
<strong>Faithful Performance Prediction of a Dynamic Task-Based Runtime System for Heterogeneous Multi-Core Architectures</strong><br/>
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<em>CCPE - Concurrency and Computation: Practice and Experience</em>, pp 16, May 2015<br/>
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[<a href="https://hal.inria.fr/hal-01147997">WWW</a>]
[<a href="https://hal.inria.fr/hal-01147997/file/CCPE14_article.pdf">PDF</a>]
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[doi:<a href="http://dx.doi.org/10.1002/cpe.3555">10.1002/cpe.3555</a>]
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<a name="stanisic:hal-01180272"></a>Luka Stanisic, Emmanuel Agullo, Alfredo Buttari, Abdou Guermouche, Arnaud Legrand, Florent Lopez,  and Brice Videau<br/>
<strong>Fast and Accurate Simulation of Multithreaded Sparse Linear Algebra Solvers</strong><br/>
In <em>The 21st IEEE International Conference on Parallel and Distributed Systems</em>, Melbourne, Australia, December 2015<br/>
[<a href="https://hal.inria.fr/hal-01180272">WWW</a>]
[<a href="https://hal.inria.fr/hal-01180272/file/QRMSTARSG_article.pdf">PDF</a>]
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<a name="stanisic:hal-01011633"></a>Luka Stanisic, Samuel Thibault, Arnaud Legrand, Brice Videau,  and Jean-François Méhaut<br/>
<strong>Modeling and Simulation of a Dynamic Task-Based Runtime System for Heterogeneous Multi-Core Architectures</strong><br/>
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In <em>Euro-Par - 20th International Conference on Parallel Processing</em>, Porto, Portugal, August 2014<br/>
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Springer-Verlag<br/>
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[<a href="http://hal.inria.fr/hal-01011633">WWW</a>]
[<a href="http://hal.inria.fr/hal-01011633/PDF/StarPUSG_article.pdf">PDF</a>]
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[doi:<a href="http://dx.doi.org/10.1007/978-3-319-09873-9_5">10.1007/978-3-319-09873-9_5</a>]
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901
<h4>On The Cell Support</h4> 
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<a name="AugThiNamNij09Samos"></a>Cédric Augonnet, Samuel Thibault, Raymond Namyst,  and Maik Nijhuis<br/>
<strong>Exploiting the Cell/BE architecture with the StarPU unified runtime system</strong><br/>
In <em>SAMOS Workshop - International Workshop on Systems, Architectures, Modeling, and Simulation</em>, volume 5657 of <em>Lecture Notes in Computer Science</em>, Samos, Greece, July 2009<br/>
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[<a href="http://hal.inria.fr/inria-00378705">WWW</a>]
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[<a href="http://hal.inria.fr/inria-00378705/document">PDF</a>]
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[doi:<a href="http://dx.doi.org/10.1007/978-3-642-03138-0_36">10.1007/978-3-642-03138-0_36</a>]
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<h4>On Applications</h4> 
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<a name="couteyencarpaye:hal-01507613"></a>Jean Marie Couteyen Carpaye, Jean Roman,  and Pierre Brenner<br/>
<strong>Design and Analysis of a Task-based Parallelization over a Runtime System of an Explicit Finite-Volume CFD Code with Adaptive Time Stepping</strong><br/>
<em>International Journal of Computational Science and Engineering</em>, pp 1 - 22, 2017<br/>
[<a href="https://hal.inria.fr/hal-01507613">WWW</a>]
[<a href="https://hal.inria.fr/hal-01507613/file/flusepa-task-hal-inria-preprint.pdf">PDF</a>]
[doi:<a href="http://dx.doi.org/10.1016/j.jocs.2017.03.008">10.1016/j.jocs.2017.03.008</a>]
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