Commit f0750471 authored by logan's avatar logan
Browse files

clean

parent 294f73ec
Pipeline #273253 failed with stages
in 20 minutes and 59 seconds
This diff is collapsed.
......@@ -46,7 +46,11 @@ struct Core {
CacheMemory<4, 16, 64>*dm, *im;
#else
CacheMemoryMulticore<4, 16, 64>*dm;
#if MCVM
CacheMemory<4, 16, 64>*im;
#else
CacheMemoryMulticoreInst<4, 16, 64>*im;
#endif
#endif
/* Registers */
......
......@@ -41,6 +41,8 @@
#define LINUXOS 0
// This variable tells the simulator where to put the DTB (for Linux)
#define DTB_BASE 0x10000
// This variable telles the simulator if we are doing a multi-core unitary test
#define MCVM 0
// This variable tells the simulator how many cores we simulate
#define NB_CORES 1
#define SMP (NB_CORES > 1)
......
......@@ -14,7 +14,7 @@
#include <elfFile.h>
#include <riscvISA.h>
#define DEBUG 0
#define DEBUG 1
BasicSimulator::BasicSimulator(std::string binaryFile,
std::vector<std::string> args,
......@@ -61,7 +61,13 @@ BasicSimulator::BasicSimulator(std::string binaryFile,
core[i].dm = new CacheMemory<4, 16, 64>(dmInterface, false);
#else
// Multi-core
#if MCVM
// One core
IncompleteMemory<4> * imInterface = new IncompleteMemory<4>(mem.data(), &reservationAMO[i]);
core[i].im = new CacheMemory<4, 16, 64>(imInterface, false);
#else
core[i].im = new CacheMemoryMulticoreInst<4, 16, 64>(new MulticoreMemory<4>(&interfaceIn[i][0], &interfaceOut[i][0], NULL), false);
#endif
core[i].dm = new CacheMemoryMulticore<4, 16, 64>(new MulticoreMemory<4>(&interfaceIn[i][1], &interfaceOut[i][1], &interfaceOut[i][2]), false);
#endif
......
......@@ -701,7 +701,7 @@ void doCycle(struct Core& core, // Core containing all values
// declare temporary register fileut
ac_int<32, false> nextInst, csrResult = 0, multResult = 0;
#if LINUXOS
#if LINUXOS || MCVM
//printf(" IM (%d)\n", (unsigned int) core.csrUnit.mhartid.slc<4>(0));
core.im->nextLevel->process(core.pc, WORD, (!localStall) ? LOAD : NONE, core.csrUnit.mhartid.slc<4>(0), 0, nextInst,
core.stallIm);
......@@ -1038,7 +1038,7 @@ void doCore(ac_int<32, false> boot_address, ac_int<4, false> mhartid, bool globa
}
#else
#elif !MCVM
// Multiple harts
void doCore(ac_int<32, false> boot_address, ac_int<4, false> mhartid,
bool globalStall, bool ir_timer, bool ipi,
......
......@@ -48,7 +48,7 @@ void doClint(Clint& clint, std::vector<ac_int<32, false> >& mem)
if (SMP)
clint.ipi[1] = (ipi_one != 0);
//printf("Timer cmp : %x vs %x %d-%d\n", p_mem[0x40], p_mem[0x4], clint.ipi[0], clint.ir_timer[0]);
//printf("Timer cmp : %x vs %x %d-%d\n", p_mem[0x40], p_mem[0x4], clint.ir_timer[1], clint.ir_timer[0]);
}
......
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