Commit eb1cd6a2 authored by Davide Pala's avatar Davide Pala
Browse files

Merge branch 'master' of gitlab.inria.fr:srokicki/Comet

Merging changes to header styles
parents 1d15e4f7 aa4057f5
Pipeline #207473 passed with stages
in 16 minutes and 31 seconds
......@@ -34,7 +34,7 @@ class CacheMemory : public MemoryInterface<INTERFACE_SIZE> {
static const int LOG_INTERFACE_SIZE = log2const<INTERFACE_SIZE>::value;
public:
MemoryInterface<INTERFACE_SIZE>* nextLevel;
IncompleteMemory<INTERFACE_SIZE>* nextLevel;
ac_int<TAG_SIZE + LINE_SIZE * 8, false> cacheMemory[SET_SIZE][ASSOCIATIVITY];
ac_int<40, false> age[SET_SIZE][ASSOCIATIVITY];
......@@ -66,7 +66,7 @@ public:
// Stats
unsigned long numberAccess, numberMiss;
CacheMemory(MemoryInterface<INTERFACE_SIZE>* nextLevel, bool v)
CacheMemory(IncompleteMemory<INTERFACE_SIZE>* nextLevel, bool v)
{
this->nextLevel = nextLevel;
for (int oneSetElement = 0; oneSetElement < SET_SIZE; oneSetElement++) {
......@@ -107,7 +107,8 @@ public:
dataOut = dataOutStore;
wasStore = false;
cacheState = 0;
waitOut = 0;
return;
} else if (opType != NONE) {
ac_int<LINE_SIZE * 8 + TAG_SIZE, false> val1 = cacheMemory[place][0];
......
This diff is collapsed.
......@@ -24,6 +24,20 @@ solution library add C28SOI_SC_12_CORE_LL_ccs -file /opt/DesignKit/catapult_lib/
go libraries
directive set -CLOCKS {clk {-CLOCK_PERIOD 2 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 1.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND sync -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_ACTIVE high}}
go assembly
directive set /doCore/core/imCache.cacheMemory:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/imCache.age:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/imCache.dataValid:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/dmCache.cacheMemory:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/dmCache.age:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/dmCache.dataValid:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/imCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/globalStall:rsc -MAP_TO_MODULE {[DirectInput]}
directive set /doCore/core/core.regFile:rsc -MAP_TO_MODULE {[Register]}
directive set /doCore/core/while -PIPELINE_INIT_INTERVAL 1
......
......@@ -24,6 +24,18 @@ solution library add Xilinx_FIFO
go libraries
directive set -CLOCKS {clk {-CLOCK_PERIOD 10.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 5.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND sync -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_ACTIVE high}}
go assembly
directive set /doCore/core/imCache.cacheMemory:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/imCache.age:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/imCache.dataValid:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/dmCache.cacheMemory:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/dmCache.age:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/dmCache.dataValid:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/imCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/globalStall:rsc -MAP_TO_MODULE {[DirectInput]}
directive set /doCore/imData:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_NOCHANGE
directive set /doCore/dmData:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_NOCHANGE
......
......@@ -24,11 +24,11 @@ BasicSimulator::BasicSimulator(std::string binaryFile, std::vector<std::string>
mem.reserve(DRAM_SIZE >> 2);
core.im = new SimpleMemory<4>(mem.data());
core.dm = new SimpleMemory<4>(mem.data());
//core.im = new SimpleMemory<4>(mem.data());
//core.dm = new SimpleMemory<4>(mem.data());
// core.im = new CacheMemory<4, 16, 64>(new SimpleMemory<4>(mem.data()), false);
// core.dm = new CacheMemory<4, 16, 64>(new SimpleMemory<4>(mem.data()), false);
core.im = new CacheMemory<4, 16, 64>(new IncompleteMemory<4>(mem.data()), false);
core.dm = new CacheMemory<4, 16, 64>(new IncompleteMemory<4>(mem.data()), false);
openFiles(inFile, outFile, tFile, sFile);
......@@ -167,6 +167,7 @@ void BasicSimulator::stb(ac_int<32, false> addr, ac_int<8, true> value)
{
ac_int<32, false> wordRes = 0;
bool stall = true;
bool releaseIDM = false;
while (stall)
core.dm->process(addr, BYTE, STORE, value, wordRes, stall);
}
......@@ -203,6 +204,7 @@ ac_int<8, true> BasicSimulator::ldb(ac_int<32, false> addr)
result = mem[addr >> 2].slc<8>(((int)addr.slc<2>(0)) << 3);
ac_int<32, false> wordRes = 0;
bool stall = true;
bool releaseIDM = false;
while (stall)
core.dm->process(addr, BYTE_U, LOAD, 0, wordRes, stall);
......
......@@ -554,8 +554,7 @@ void doCycle(struct Core& core, // Core containing all values
// declare temporary register file
ac_int<32, false> nextInst;
if (!localStall && !core.stallDm)
core.im->process(core.pc, WORD, LOAD, 0, nextInst, core.stallIm);
core.im->process(core.pc, WORD, (!localStall && !core.stallDm) ? LOAD : NONE, 0, nextInst, core.stallIm);
fetch(core.pc, ftoDC_temp, nextInst);
decode(core.ftoDC, dctoEx_temp, core.regFile);
......@@ -570,34 +569,35 @@ void doCycle(struct Core& core, // Core containing all values
memtoWB_temp.rd, memtoWB_temp.useRd, wbOut_temp.rd, wbOut_temp.useRd, core.stallSignals,
forwardRegisters);
if (!core.stallSignals[STALL_MEMORY] && !localStall && memtoWB_temp.we && !core.stallIm) {
memMask mask;
// TODO: carry the data size to memToWb
switch (core.extoMem.funct3) {
case 0:
mask = BYTE;
break;
case 1:
mask = HALF;
break;
case 2:
mask = WORD;
break;
case 4:
mask = BYTE_U;
break;
case 5:
mask = HALF_U;
break;
// Should NEVER happen
default:
mask = WORD;
break;
}
core.dm->process(memtoWB_temp.address, mask, memtoWB_temp.isLoad ? LOAD : (memtoWB_temp.isStore ? STORE : NONE),
memtoWB_temp.valueToWrite, memtoWB_temp.result, core.stallDm);
memMask mask;
// TODO: carry the data size to memToWb
switch (core.extoMem.funct3) {
case 0:
mask = BYTE;
break;
case 1:
mask = HALF;
break;
case 2:
mask = WORD;
break;
case 4:
mask = BYTE_U;
break;
case 5:
mask = HALF_U;
break;
// Should NEVER happen
default:
mask = WORD;
break;
}
memOpType opType = (!core.stallSignals[STALL_MEMORY] && !localStall && memtoWB_temp.we && !core.stallIm && memtoWB_temp.isLoad) ? LOAD
: (!core.stallSignals[STALL_MEMORY] && !localStall && memtoWB_temp.we && !core.stallIm && memtoWB_temp.isStore ? STORE : NONE);
core.dm->process(memtoWB_temp.address, mask, opType, memtoWB_temp.valueToWrite, memtoWB_temp.result, core.stallDm);
// commit the changes to the pipeline register
if (!core.stallSignals[STALL_FETCH] && !localStall && !core.stallIm && !core.stallDm) {
core.ftoDC = ftoDC_temp;
......@@ -663,10 +663,11 @@ void doCore(bool globalStall, ac_int<32, false> imData[1 << 24], ac_int<32, fals
IncompleteMemory<4> imInterface = IncompleteMemory<4>(imData);
IncompleteMemory<4> dmInterface = IncompleteMemory<4>(dmData);
// CacheMemory<4, 16, 64> dmCache = CacheMemory<4, 16, 64>(&dmInterface, false);
CacheMemory<4, 16, 64> dmCache = CacheMemory<4, 16, 64>(&dmInterface, false);
CacheMemory<4, 16, 64> imCache = CacheMemory<4, 16, 64>(&imInterface, false);
core.im = &imInterface;
core.dm = &dmInterface;
core.im = &imCache;
core.dm = &dmCache;
core.pc = 0;
while (1) {
......
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