Commit bfdc83fb authored by logan's avatar logan
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new docs

parent 0c343a8a
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......@@ -169,10 +169,6 @@ RTL synthesis is tested using [Mentor Catapult HLS](
./generateBin /path/to/your/elf/file/zephyr.elf > /path/to/your/rtl/simulation//zephyr.bin
Using the RTL simulator you want, you should be able to see something like this:
![RTL OS Boot](./docs/demo_RTL.png)
## Publication
- "<a href="">What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications</a>", in 38th IEEE/ACM International Conference on Computer-Aided Design
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