Commit bb38ca2d authored by FORTUNE Logan's avatar FORTUNE Logan

rtl working

parent 4ba51bb6
Pipeline #235547 failed with stages
in 1 minute and 18 seconds
......@@ -71,7 +71,7 @@ begin
else
mtime_d <= mtime_d + 1;
mtime_o <= mtime_d;
if(en_i = '1') then
if en_i = '1' then
mtimecmp <= timer_interrupt_i;
else
mtimecmp <= mtimecmp;
......
......@@ -30,7 +30,7 @@ entity directory is
port(
clk_i : in std_logic;
reset_i : in std_logic;
dmData_rsc_adr_i : in std_logic_vector(23 downto 0);
dmData_rsc_adr_i : in std_logic_vector(18 downto 0);
dmData_rsc_d_i : in std_logic_vector(31 downto 0);
dmData_rsc_we_i : in std_logic;
dmData_rsc_en_i : in std_logic;
......@@ -40,7 +40,7 @@ entity directory is
ARM_en_i: in std_logic;
-- Memory Interface
dmData_rsc_q_o : out std_logic_vector(31 downto 0);
memory_rsc_adr_o : out std_logic_vector(23 downto 0);
memory_rsc_adr_o : out std_logic_vector(18 downto 0);
memory_rsc_d_o : out std_logic_vector(31 downto 0);
memory_rsc_q_i : in std_logic_vector(31 downto 0);
memory_rsc_we_o : out std_logic;
......@@ -71,7 +71,7 @@ architecture directory_arch of directory is
signal special_request : std_logic;
begin
memory_rsc_adr_o <= ARM_addr_i when ARM_en_i = '1' else dmData_rsc_adr_i;
memory_rsc_adr_o <= ARM_addr_i(18 downto 0) when ARM_en_i = '1' else dmData_rsc_adr_i;
memory_rsc_d_o <= ARM_din_i when ARM_en_i = '1' else dmData_rsc_d_i;
memory_rsc_we_o <= ARM_we_i when ARM_en_i= '1' else dmData_rsc_we_i;
memory_rsc_en_o <= '1';
......@@ -87,17 +87,19 @@ begin
en_timer_o <= '0';
timer_interrupt_o <= (others => '0');
else
if dmData_rsc_adr_i = x"10" and dmData_rsc_en_i = '1' then
if dmData_rsc_adr_i(18 downto 0) = x"00004" and dmData_rsc_en_i = '1' then
directory_dmData_rsc_q <= mtime_i(31 downto 0);-- read mtime
special_request <= '1';
elsif dmData_rsc_adr_i = x"14" and dmData_rsc_en_i = '1' then
en_timer_o <= '0';
elsif dmData_rsc_adr_i(18 downto 0) = x"00005" and dmData_rsc_en_i = '1' then
directory_dmData_rsc_q <= mtime_i(63 downto 32);-- read mtime
special_request <= '1';
elsif dmData_rsc_adr_i = x"250" and dmData_rsc_we_i = '1' then
en_timer_o <= '0';
elsif dmData_rsc_adr_i(18 downto 0) = x"00040" and dmData_rsc_we_i = '1' then
timer_interrupt_o(31 downto 0) <= dmData_rsc_d_i;
en_timer_o <= '1';
special_request <= '0';
elsif dmData_rsc_adr_i = x"254" and dmData_rsc_we_i = '1' then
elsif dmData_rsc_adr_i(18 downto 0) = x"00041" and dmData_rsc_we_i = '1' then
timer_interrupt_o(63 downto 32) <= dmData_rsc_d_i;
en_timer_o <= '1';
special_request <= '0';
......
......@@ -71,21 +71,20 @@ architecture arch of tb_comet is
signal ipi : std_logic:='0';
-- MEMORY
signal boot_address : std_logic_vector (31 downto 0) := x"00030000";
signal memory_rsc_adr : std_logic_vector (23 DOWNTO 0);
signal memory_rsc_adr : std_logic_vector (18 DOWNTO 0);
signal memory_rsc_d : std_logic_vector (31 DOWNTO 0);
signal memory_rsc_we : std_logic:='0';
signal memory_rsc_q : std_logic_vector (31 DOWNTO 0);
signal memory_rsc_en : std_logic:='0';
signal memory_rsc_adr_19 : std_logic_vector (18 downto 0);
--signal memory_rsc_adr_19 : std_logic_vector (18 downto 0);
signal imData_rsc_adr : std_logic_vector (23 downto 0);
signal imData_rsc_adr_19 : std_logic_vector (18 downto 0);
signal imData_rsc_adr : std_logic_vector (18 downto 0);
--signal imData_rsc_adr_19 : std_logic_vector (18 downto 0);
signal imData_rsc_q : std_logic_vector (31 downto 0);
signal imData_rsc_d : std_logic_vector (31 downto 0);
signal imData_rsc_we : std_logic:='0';
signal imData_rsc_en : std_logic:='0';
signal dmData_rsc_adr : std_logic_vector (23 downto 0);
--signal dmData_rsc_adr_19 : std_logic_vector (23 downto 0):= (others=>'0');
signal dmData_rsc_adr : std_logic_vector (18 downto 0);
signal dmData_rsc_q : std_logic_vector (31 downto 0);
signal dmData_rsc_d : std_logic_vector (31 downto 0);
signal dmData_rsc_we : std_logic:='0';
......@@ -96,10 +95,6 @@ architecture arch of tb_comet is
signal ARM_din : std_logic_vector(31 downto 0):= (others=>'0');
signal ARM_en : std_logic:='0';
--FSM Memory Stall
signal imData_adr_mem : std_logic_vector (23 downto 0):= (others=>'0');
signal dmData_adr_mem : std_logic_vector (23 downto 0):= (others=>'0');
type status is (OK, TOO_LOW, TOO_HIGH);
signal add_inst_status : status;
signal add_data_status : status;
......@@ -152,8 +147,8 @@ begin
clk => clk,
en => en_comet,
mhartid_rsc_dat => mhartid,
ir_timer_rsc_dat=> '0',
ipi_rsc_dat => '0',
ir_timer => ir_timer,
ipi => '0',
rst => rst,
boot_address_rsc_dat => boot_address,
globalStall => globalStall,
......@@ -216,24 +211,19 @@ begin
memory_data : entity work.design_1_blk_mem_gen_1_0
port map(
clka => clk,
--rsta => rst,
ena => imData_rsc_en,
wea(0) => imData_rsc_we,
addra => imData_rsc_adr_19,
addra => imData_rsc_adr,
dina => imData_rsc_d,
douta => imData_rsc_q,
clkb => clk,
--rstb => rst,
enb => '1',
web(0) => memory_rsc_we,
addrb => memory_rsc_adr_19,
addrb => memory_rsc_adr,
dinb => memory_rsc_d,
doutb => memory_rsc_q
--rsta_busy => open,
--rstb_busy => open
);
imData_rsc_adr_19 <= imData_rsc_adr(18 downto 0);
memory_rsc_adr_19 <= memory_rsc_adr(18 downto 0);
--
----------------------------------------------------------------------------
-- Combi
......@@ -243,33 +233,18 @@ begin
TOO_HIGH when ARM_addr > ADD_MAX_INSTRUCTION else
OK;
add_data_status <= TOO_LOW when memory_rsc_adr < ADD_MIN_DATA and dmData_rsc_adr/= x"000000" else
add_data_status <= TOO_LOW when memory_rsc_adr < ADD_MIN_DATA and dmData_rsc_adr(15 downto 0) /= x"0000" else
TOO_HIGH when memory_rsc_adr > ADD_MAX_DATA else OK;
--
--we_data_mem <= dmData_rsc_we when dmData_rsc_adr/= x"0C0000" and dmData_rsc_adr/= x"0C0001" else '0'; -- To not write in data memory when we update a status or write character out
--end_of_test <= dmData_rsc_d(BIT_POS_EOT) when dmData_rsc_adr= x"0C0001" and dmData_rsc_we = '1' else '0'; -- create end of test
--hang <= dmData_rsc_d(BIT_POS_HANG) when dmData_rsc_adr= x"0C0001" and dmData_rsc_we = '1' else '0';
--crash <= dmData_rsc_d(BIT_POS_CRASH)when dmData_rsc_adr= x"0C0001" and dmData_rsc_we = '1' else '0';
char_out <= memory_rsc_d when memory_rsc_adr(19 downto 0) = x"001E4" and memory_rsc_we = '1' and memory_rsc_d /= x"0000001B" else char_out_q;-- when dmData_rsc_adr= x"0C0000" and dmData_rsc_we = '1' else (others => '0');
char_out <= memory_rsc_d when memory_rsc_adr(15 downto 0) = x"01E4" and memory_rsc_we = '1' and memory_rsc_d /= x"0000001B" else char_out_q;
----------------------------------------------------------------------------
-- Stimuli
----------------------------------------------------------------------------
-- generate clocks
clk <= not clk after CLK_PERIOD/2;
--MemoryStallFSM : process(clk)
--begin
-- if rising_edge(clk) then
-- if imData_adr_mem /= imData_rsc_adr or dmData_adr_mem /= dmData_rsc_adr then
-- en_comet <= '0';
-- else
-- en_comet <= '1';
-- end if;
-- end if;
--end process;
Stimuli : process
variable line_num0 : line;
......@@ -279,8 +254,6 @@ begin
file file_stimuli : text;
begin
imData_adr_mem <= imData_rsc_adr;
dmData_adr_mem <= dmData_rsc_adr;
rst <= '1';
globalStall <= '1';
en_comet <= '0';
......@@ -290,7 +263,7 @@ begin
-- Fill memory
ARM_en <= '1';
file_open(file_stimuli,"../../../../../zephyr.bin", READ_MODE); -- zephyr bin
file_open(file_stimuli,"../../../../../zephyr_synch.bin", READ_MODE); -- zephyr bin
while not endfile(file_stimuli) loop
readline(file_stimuli, line_num0);
if character(line_num0(1)) /= ';' then --jump commented lines
......@@ -318,7 +291,7 @@ file file_result : text open write_mode is "../../../../../results.txt";
begin
if rising_edge(clk) then
char_out_q <= char_out;
if memory_rsc_adr(19 downto 0)= x"001E4" and memory_rsc_we = '1' then -- UART_RXTX
if memory_rsc_adr(15 downto 0)= x"01E4" and memory_rsc_we = '1' then -- UART_RXTX
hwrite(line_num1,char_out);
writeline(file_result,line_num1);
end if;
......@@ -331,16 +304,14 @@ variable line_num_i : line;
file file_dump_d : text open write_mode is "../../../../../dump_add_data.txt";
file file_dump_i : text open write_mode is "../../../../../dump_add_inst.txt";
begin
if rising_edge(clk) and dmData_rsc_en = '1' then
if rising_edge(clk) and imData_rsc_en = '1' and globalStall = '0' then
counter <= counter + 1;
hwrite(line_num_d,dmData_rsc_adr);
STD.TEXTIO.write(line_num_d,string'(" "));
hwrite(line_num_i,imData_rsc_adr);
STD.TEXTIO.write(line_num_i,string'(" "));
if counter(2 downto 0) = "111" then
writeline(file_dump_d,line_num_d);
writeline(file_dump_i,line_num_i);
end if;
writeline(file_dump_d,line_num_d);
writeline(file_dump_i,line_num_i);
end if;
end process;
......
#Python program to compare the testbench from the emulation and the testbench from the RTL simulation
# Using readlines()
file1 = open('debug.txt', 'r')
file2 = open('dump_add_inst.txt', 'r')
LinesDebug = file1.readlines()
LinesRTL = file2.readlines()
diff = 0
count = 0
count_line = 0
# Strips the newline character
for line in LinesRTL:
count_line += 1
# Convert hex string to hex with RTL debug
line = "0x"+line
line_integer = int(line, 16)
line_integer = line_integer<<2
hex_value = hex(line_integer)
# Parse debug file
can_be_compared = -1
while(can_be_compared < 0):
can_be_compared = LinesDebug[count].find("[0]") + LinesDebug[count].find("[1]")
if can_be_compared < 0:
count += 1
line_debug_to_compare = LinesDebug[count][LinesDebug[count].find(":")+1:LinesDebug[count].find("[")]
line_debug_to_compare = "0x"+ line_debug_to_compare.replace(" ", "")
line_debug_to_compare = int(line_debug_to_compare, 16)
hex_value_debug = hex(line_debug_to_compare)
if(hex_value != hex_value_debug):
diff += 1
print("* Line{}: (rtl){} vs (debug){}".format(count_line, hex_value, hex_value_debug))
else:
print("= Line{}: (rtl){} vs (debug){}".format(count_line, hex_value, hex_value_debug))
count += 1
if diff != 0:
print(diff)
diff = 0
if diff > 10:
break;
file1.close()
file2.close()
......@@ -388,7 +388,7 @@ public:
}
}
}
this->nextLevel->process(nextLevelAddr, LONG, nextLevelOpType, hartid, nextLevelDataIn, nextLevelDataOut, nextLevelWaitOut);
this->nextLevel->process(nextLevelAddr, WORD, nextLevelOpType, hartid, nextLevelDataIn, nextLevelDataOut, nextLevelWaitOut);
waitOut = nextLevelWaitOut || cacheState || wasStore;
}
};
......
......@@ -34,9 +34,9 @@
*/
// This variable tells the simulator if we are using a bare-metal program or an OS: 0->bare-metal 1->OS
#define HAS_KERNEL_SYSCALL_HANDLER 1
#define HAS_KERNEL_SYSCALL_HANDLER 0
// This variable tells the simulator if we are using the console or not (1->console enable)
#define PRINT_CONSOLE 1
#define PRINT_CONSOLE 0
// This variable tells the simulator how many cores we simulate
#define NB_CORES 1
// Memory size
......
......@@ -22,7 +22,7 @@ go compile
solution library add ccs_sample_mem -- -rtlsyntool DesignCompiler -vendor STMicroelectronics -technology {28nm FDSOI}
solution library add C28SOI_SC_12_CORE_LL_ccs -file /opt/DesignKit/catapult_lib/C28SOI_SC_12_CORE_LL_ccs.lib
go libraries
directive set -CLOCKS {clk {-CLOCK_PERIOD 2 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 1.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND sync -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
directive set -CLOCKS {clk {-CLOCK_PERIOD 10.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 5.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND sync -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
go assembly
directive set /doCore/core/imCache.cacheMemory:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/imCache.age:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
......@@ -42,7 +42,8 @@ directive set /doCore/core/dmCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.dirtyBit:rsc -INTERLEAVE 4
directive set /doCore/ir_timer:rsc -MAP_TO_MODULE {[DirectInput]}
directive set /doCore/ipi:rsc -MAP_TO_MODULE {[DirectInput]}
directive set /doCore/globalStall:rsc -MAP_TO_MODULE {[DirectInput]}
directive set /doCore/core/core.regFile:rsc -MAP_TO_MODULE {[Register]}
directive set /doCore/core/while -PIPELINE_INIT_INTERVAL 1
......
......@@ -24,23 +24,25 @@ solution library add Xilinx_FIFO
go libraries
directive set -CLOCKS {clk {-CLOCK_PERIOD 10.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 5.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND sync -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
go assembly
#directive set /doCore/core/imCache.cacheMemory:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
#directive set /doCore/core/imCache.age:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
#directive set /doCore/core/imCache.dataValid:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
#directive set /doCore/core/imCache.dirtyBit:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
#directive set /doCore/core/dmCache.cacheMemory:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
#directive set /doCore/core/dmCache.age:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
#directive set /doCore/core/dmCache.dataValid:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
#directive set /doCore/core/dmCache.dirtyBit:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
#directive set /doCore/core/imCache.cacheMemory:rsc -INTERLEAVE 4
#directive set /doCore/core/imCache.age:rsc -INTERLEAVE 4
#directive set /doCore/core/imCache.dataValid:rsc -INTERLEAVE 4
#directive set /doCore/core/imCache.dirtyBit:rsc -INTERLEAVE 4
#directive set /doCore/core/dmCache.cacheMemory:rsc -INTERLEAVE 4
#directive set /doCore/core/dmCache.age:rsc -INTERLEAVE 4
#directive set /doCore/core/dmCache.dataValid:rsc -INTERLEAVE 4
#directive set /doCore/core/dmCache.dirtyBit:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.cacheMemory:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/imCache.age:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/imCache.dataValid:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/imCache.dirtyBit:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/dmCache.cacheMemory:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/dmCache.age:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/dmCache.dataValid:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/dmCache.dirtyBit:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/imCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.dirtyBit:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.dirtyBit:rsc -INTERLEAVE 4
directive set /doCore/globalStall:rsc -MAP_TO_MODULE {[DirectInput]}
directive set /doCore/ir_timer:rsc -MAP_TO_MODULE {[DirectInput]}
directive set /doCore/ipi:rsc -MAP_TO_MODULE {[DirectInput]}
directive set /doCore/imData:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_NOCHANGE
directive set /doCore/dmData:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_NOCHANGE
directive set /doCore/core/core.regFile:rsc -MAP_TO_MODULE {[Register]}
......
......@@ -28,10 +28,10 @@ BasicSimulator::BasicSimulator(std::string binaryFile, std::vector<std::string>
// Init Core PC
core[i].regFile[2] = STACK_INIT;
core[i].csrUnit.mhartid = ac_int<4, false>(i);
//core[i].im = new CacheMemory<4, 16, 64>(new IncompleteMemory<4>(mem.data()), false);
//core[i].dm = new CacheMemory<4, 16, 64>(new IncompleteMemory<4>(mem.data()), false);
core[i].im = new IncompleteMemory<4>(mem.data());
core[i].dm = new IncompleteMemory<4>(mem.data());
core[i].im = new CacheMemory<4, 16, 64>(new IncompleteMemory<4>(mem.data()), false);
core[i].dm = new CacheMemory<4, 16, 64>(new IncompleteMemory<4>(mem.data()), false);
//core[i].im = new IncompleteMemory<4>(mem.data());
//core[i].dm = new IncompleteMemory<4>(mem.data());
clint.ir_timer[i] = 0;
clint.ipi[i] = 0;
}
......
......@@ -857,11 +857,11 @@ void doCore(ac_int<32, false> boot_address, ac_int<4, false> mhartid, bool globa
IncompleteMemory<4> imInterface = IncompleteMemory<4>(imData);
IncompleteMemory<4> dmInterface = IncompleteMemory<4>(dmData);
//CacheMemory<4, 16, 64> dmCache = CacheMemory<4, 16, 64>(&dmInterface, false);
//CacheMemory<4, 16, 64> imCache = CacheMemory<4, 16, 64>(&imInterface, false);
CacheMemory<4, 16, 64> dmCache = CacheMemory<4, 16, 64>(&dmInterface, false);
CacheMemory<4, 16, 64> imCache = CacheMemory<4, 16, 64>(&imInterface, false);
core.im = &imInterface;
core.dm = &dmInterface;
core.im = &imCache;
core.dm = &dmCache;
// Init
core.pc = boot_address;
......
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