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Commit aa4057f5 authored by FORTUNE Logan's avatar FORTUNE Logan

instruction+data cache HLS Asic/Xilinx passed

parent 5e1bddd4
Pipeline #207012 passed with stages
in 16 minutes and 27 seconds
......@@ -86,7 +86,7 @@ public:
}
void process(ac_int<32, false> addr, memMask mask, memOpType opType, ac_int<INTERFACE_SIZE * 8, false> dataIn,
ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut, bool& releaseIDM)
ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut)
{
// bit size is the log(setSize)
......@@ -355,9 +355,8 @@ public:
}
}
this->nextLevel->process(nextLevelAddr, LONG, nextLevelOpType, nextLevelDataIn, nextLevelDataOut, nextLevelWaitOut, nextLevelWaitOut);
this->nextLevel->process(nextLevelAddr, LONG, nextLevelOpType, nextLevelDataIn, nextLevelDataOut, nextLevelWaitOut);
waitOut = nextLevelWaitOut || cacheState || (wasStore && opType != NONE);
releaseIDM = nextLevelWaitOut || (cacheState != 0 && cacheState != 1);
}
};
......
......@@ -40,7 +40,6 @@ struct Core {
// stall
bool stallSignals[5] = {0, 0, 0, 0, 0};
bool stallIm, stallDm;
bool releaseIM, releaseDM;
unsigned long cycle;
/// Multicycle operation
......
......@@ -13,7 +13,7 @@ protected:
public:
virtual void process(ac_int<32, false> addr, memMask mask, memOpType opType, ac_int<INTERFACE_SIZE * 8, false> dataIn,
ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut, bool& releaseIDM) = 0;
ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut) = 0;
};
template <unsigned int INTERFACE_SIZE> class IncompleteMemory : public MemoryInterface<INTERFACE_SIZE> {
......@@ -23,7 +23,7 @@ public:
public:
IncompleteMemory(ac_int<32, false>* arg) { data = arg; }
void process(ac_int<32, false> addr, memMask mask, memOpType opType, ac_int<INTERFACE_SIZE * 8, false> dataIn,
ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut, bool& releaseIDM)
ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut)
{
// Incomplete memory only works for 32 bits
......@@ -31,7 +31,6 @@ public:
// no latency, wait is always set to false
waitOut = false;
releaseIDM = false;
if (opType == STORE) {
data[(addr >> 2) & 0xffffff] = dataIn;
} else if (opType == LOAD) {
......
......@@ -24,6 +24,18 @@ solution library add Xilinx_FIFO
go libraries
directive set -CLOCKS {clk {-CLOCK_PERIOD 10.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 5.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND sync -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_ACTIVE high}}
go assembly
directive set /doCore/core/imCache.cacheMemory:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/imCache.age:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/imCache.dataValid:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/dmCache.cacheMemory:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/dmCache.age:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/dmCache.dataValid:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/imCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/globalStall:rsc -MAP_TO_MODULE {[DirectInput]}
directive set /doCore/imData:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_NOCHANGE
directive set /doCore/dmData:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_NOCHANGE
......
......@@ -169,7 +169,7 @@ void BasicSimulator::stb(ac_int<32, false> addr, ac_int<8, true> value)
bool stall = true;
bool releaseIDM = false;
while (stall)
core.dm->process(addr, BYTE, STORE, value, wordRes, stall, releaseIDM);
core.dm->process(addr, BYTE, STORE, value, wordRes, stall);
}
void BasicSimulator::sth(ac_int<32, false> addr, ac_int<16, true> value)
......@@ -206,7 +206,7 @@ ac_int<8, true> BasicSimulator::ldb(ac_int<32, false> addr)
bool stall = true;
bool releaseIDM = false;
while (stall)
core.dm->process(addr, BYTE_U, LOAD, 0, wordRes, stall, releaseIDM);
core.dm->process(addr, BYTE_U, LOAD, 0, wordRes, stall);
result = wordRes.slc<8>(0);
return result;
......
......@@ -516,8 +516,6 @@ void doCycle(struct Core& core, // Core containing all values
core.stallSignals[4] = 0;
core.stallIm = false;
core.stallDm = false;
core.releaseIM = false;
core.releaseDM = false;
// declare temporary structs
struct FtoDC ftoDC_temp;
......@@ -559,7 +557,7 @@ void doCycle(struct Core& core, // Core containing all values
// declare temporary register file
ac_int<32, false> nextInst;
core.im->process(core.pc, WORD, (!localStall && !core.releaseIM) ? LOAD : NONE, 0, nextInst, core.stallIm, core.releaseDM);
core.im->process(core.pc, WORD, (!localStall && !core.stallDm) ? LOAD : NONE, 0, nextInst, core.stallIm);
fetch(core.pc, ftoDC_temp, nextInst);
decode(core.ftoDC, dctoEx_temp, core.regFile);
......@@ -598,10 +596,10 @@ void doCycle(struct Core& core, // Core containing all values
break;
}
memOpType opType = (!core.stallSignals[STALL_MEMORY] && !localStall && memtoWB_temp.we && !core.releaseDM && memtoWB_temp.isLoad) ? LOAD
: (!core.stallSignals[STALL_MEMORY] && !localStall && memtoWB_temp.we && !core.releaseDM && memtoWB_temp.isStore ? STORE : NONE);
memOpType opType = (!core.stallSignals[STALL_MEMORY] && !localStall && memtoWB_temp.we && !core.stallIm && memtoWB_temp.isLoad) ? LOAD
: (!core.stallSignals[STALL_MEMORY] && !localStall && memtoWB_temp.we && !core.stallIm && memtoWB_temp.isStore ? STORE : NONE);
core.dm->process(memtoWB_temp.address, mask, opType, memtoWB_temp.valueToWrite, memtoWB_temp.result, core.stallDm, core.releaseIM);
core.dm->process(memtoWB_temp.address, mask, opType, memtoWB_temp.valueToWrite, memtoWB_temp.result, core.stallDm);
// commit the changes to the pipeline register
if (!core.stallSignals[STALL_FETCH] && !localStall && !core.stallIm && !core.stallDm) {
......
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