Add template on memory interface

-> have to remove memoryInterface.cpp 
-> A template control interface Byte width
-> Cache can also be configured more precisely

CMakeLists.txt

@@ -13,14 +13,12 @@ add_executable(comet.sim
 							./src/elfFile.cpp
 							./src/main.cpp
 							./src/riscvISA.cpp
-							./src/basic_simulator.cpp
-							./src/memoryInterface.cpp)
+							./src/basic_simulator.cpp)
 
 add_executable(atomicTests
 							./src/core.cpp
 							./src/atomicTest.cpp
 							./src/elfFile.cpp
-							./src/riscvISA.cpp
-							./src/memoryInterface.cpp)
+							./src/riscvISA.cpp)
 
 #target_link_libraries( comet.sim	LINK_PUBLIC ${Boost_LIBRARIES} )

include/core.h

@@ -31,7 +31,8 @@ struct Core {
   ExtoMem extoMem;
   MemtoWB memtoWB;
 
-  MemoryInterface *dm, *im;
+  // Interface size are configured with 4 bytes interface size (32 bits)
+  MemoryInterface<4>*dm, *im;
 
   ac_int<32, true> regFile[32];
   ac_int<32, false> pc;

include/logarithm.h

+template <int x> struct log2const {
+  enum { value = 1 + log2const<x / 2>::value };
+};
+
+template <> struct log2const<1> {
+  enum { value = 0 };
+};

include/memoryInterface.h

@@ -3,37 +3,114 @@
 
 #include <ac_int.h>
 
-typedef enum { BYTE = 0, HALF, WORD, BYTE_U, HALF_U } memMask;
+typedef enum { BYTE = 0, HALF, WORD, BYTE_U, HALF_U, LONG } memMask;
 
 typedef enum { NONE = 0, LOAD, STORE } memOpType;
 
-class MemoryInterface {
+template <unsigned int INTERFACE_SIZE> class MemoryInterface {
 protected:
   bool wait;
 
 public:
-  virtual void process(ac_int<32, false> addr, memMask mask, memOpType opType, ac_int<32, false> dataIn,
-                       ac_int<32, false>& dataOut, bool& waitOut) = 0;
+  virtual void process(ac_int<32, false> addr, memMask mask, memOpType opType, ac_int<INTERFACE_SIZE * 8, false> dataIn,
+                       ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut) = 0;
 };
 
-class IncompleteMemory : public MemoryInterface {
+template <unsigned int INTERFACE_SIZE> class IncompleteMemory : public MemoryInterface<INTERFACE_SIZE> {
 public:
   ac_int<32, false>* data;
 
 public:
   IncompleteMemory(ac_int<32, false>* arg) { data = arg; }
+  void process(ac_int<32, false> addr, memMask mask, memOpType opType, ac_int<INTERFACE_SIZE * 8, false> dataIn,
+               ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut)
+  {
 
-  void process(ac_int<32, false> addr, memMask mask, memOpType opType, ac_int<32, false> dataIn,
-               ac_int<32, false>& dataOut, bool& waitOut);
+    // Incomplete memory only works for 32 bits
+    assert(INTERFACE_SIZE == 4);
+
+    // no latency, wait is always set to false
+    waitOut = false;
+    if (opType == STORE) {
+      data[addr >> 2] = dataIn;
+    } else if (opType == LOAD) {
+      dataOut = data[addr >> 2];
+    }
+  }
 };
 
-class SimpleMemory : public MemoryInterface {
+template <unsigned int INTERFACE_SIZE> class SimpleMemory : public MemoryInterface<INTERFACE_SIZE> {
 public:
   ac_int<32, false>* data;
 
   SimpleMemory(ac_int<32, false>* arg) { data = arg; }
-  void process(ac_int<32, false> addr, memMask mask, memOpType opType, ac_int<32, false> dataIn,
-               ac_int<32, false>& dataOut, bool& waitOut);
+  void process(ac_int<32, false> addr, memMask mask, memOpType opType, ac_int<INTERFACE_SIZE * 8, false> dataIn,
+               ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut)
+  {
+    // no latency, wait is always set to false
+
+    ac_int<32, true> temp;
+    ac_int<8, false> t8;
+    ac_int<1, true> bit;
+    ac_int<16, false> t16;
+
+    switch (opType) {
+      case STORE:
+        switch (mask) {
+          case BYTE_U:
+          case BYTE:
+            temp = data[addr >> 2];
+            data[addr >> 2].set_slc(((int)addr.slc<2>(0)) << 3, dataIn.template slc<8>(0));
+            break;
+          case HALF:
+          case HALF_U:
+            temp = data[addr >> 2];
+            data[addr >> 2].set_slc(addr[1] ? 16 : 0, dataIn.template slc<16>(0));
+
+            break;
+          case WORD:
+            temp            = data[addr >> 2];
+            data[addr >> 2] = dataIn;
+            break;
+          case LONG:
+            for (int oneWord = 0; oneWord < INTERFACE_SIZE / 4; oneWord++)
+              data[(addr >> 2) + oneWord] = dataIn.template slc<32>(32 * oneWord);
+            break;
+        }
+        break;
+      case LOAD:
+        switch (mask) {
+          case BYTE:
+            t8  = data[addr >> 2].slc<8>(((int)addr.slc<2>(0)) << 3);
+            bit = t8.slc<1>(7);
+            dataOut.set_slc(0, t8);
+            dataOut.set_slc(8, (ac_int<24, true>)bit);
+            break;
+          case HALF:
+            t16 = data[addr >> 2].slc<16>(addr[1] ? 16 : 0);
+            bit = t16.slc<1>(15);
+            dataOut.set_slc(0, t16);
+            dataOut.set_slc(16, (ac_int<16, true>)bit);
+            break;
+          case WORD:
+            dataOut = data[addr >> 2];
+            break;
+          case LONG:
+            for (int oneWord = 0; oneWord < INTERFACE_SIZE / 4; oneWord++)
+              dataOut.set_slc(32 * oneWord, data[(addr >> 2) + oneWord]);
+            break;
+          case BYTE_U:
+            dataOut = data[addr >> 2].slc<8>(((int)addr.slc<2>(0)) << 3) & 0xff;
+            break;
+          case HALF_U:
+            dataOut = data[addr >> 2].slc<16>(addr[1] ? 16 : 0) & 0xffff;
+            break;
+        }
+
+        break;
+    }
+    waitOut = false;
+  }
 };
 
 #endif //__MEMORY_INTERFACE_H__

scripts/catapult_xilinx.tcl

@@ -10,7 +10,6 @@ solution options set /Input/CompilerFlags {-D __CATAPULT__ -D __HLS__ -D MEMORY_
 solution options set /Input/SearchPath $WORKING_DIR/../include
 solution options set /Output/GenerateCycleNetlist false
 solution file add $WORKING_DIR/../src/core.cpp -type C++
-solution file add $WORKING_DIR/../src/memoryInterface.cpp -type C++
 
 directive set -DESIGN_GOAL area
 

src/atomicTest.cpp

@@ -78,8 +78,8 @@ int main(int argc, char** argv)
     Core core;
     ac_int<32, false> im[8192], dm[8192];
 
-    core.im = new CacheMemory(new IncompleteMemory(im), false);
-    core.dm = new CacheMemory(new IncompleteMemory(dm), true);
+    core.im = new CacheMemory<4, 16, 64>(new IncompleteMemory<4>(im), false);
+    core.dm = new CacheMemory<4, 16, 64>(new IncompleteMemory<4>(dm), true);
 
     core.pc = initialState.pc;
     for (int oneReg = 0; oneReg < 32; oneReg++)

src/basic_simulator.cpp

@@ -21,11 +21,11 @@ BasicSimulator::BasicSimulator(const char* binaryFile, std::vector<std::string>
 
   core.cycle = 0;
 
-  // core.im = new SimpleMemory(im);
-  // core.dm = new SimpleMemory(dm);
+  // core.im = new SimpleMemory<4>(im);
+  // core.dm = new SimpleMemory<4>(dm);
 
-  core.im = new CacheMemory(new SimpleMemory(im), false);
-  core.dm = new CacheMemory(new SimpleMemory(dm), false);
+  core.im = new CacheMemory<4, 16, 64>(new SimpleMemory<4>(im), false);
+  core.dm = new CacheMemory<4, 16, 64>(new SimpleMemory<4>(dm), false);
 
   for (int i = 0; i < 32; i++) {
     core.regFile[i] = 0;

src/core.cpp

@@ -743,8 +743,8 @@ void doCycle(struct Core& core, // Core containing all values
 void doCore(bool globalStall, ac_int<32, false> imData[8192], ac_int<32, false> dmData[8192])
 {
   Core core;
-  IncompleteMemory imInterface = IncompleteMemory(imData);
-  IncompleteMemory dmInterface = IncompleteMemory(dmData);
+  IncompleteMemory<4> imInterface = IncompleteMemory<4>(imData);
+  IncompleteMemory<4> dmInterface = IncompleteMemory<4>(dmData);
 
   //    CacheMemory dmCache = CacheMemory(&dmInterface, false);
 

src/memoryInterface.cpp

-#include <memoryInterface.h>
-
-void IncompleteMemory::process(ac_int<32, false> addr, memMask mask, memOpType opType, ac_int<32, false> dataIn,
-                               ac_int<32, false>& dataOut, bool& waitOut)
-{
-  // no latency, wait is always set to false
-  waitOut = false;
-  if (opType == STORE) {
-    data[addr >> 2] = dataIn;
-  } else if (opType == LOAD) {
-    dataOut = data[addr >> 2];
-  }
-}
-
-void SimpleMemory::process(ac_int<32, false> addr, memMask mask, memOpType opType, ac_int<32, false> dataIn,
-                           ac_int<32, false>& dataOut, bool& waitOut)
-{
-  // no latency, wait is always set to false
-
-  ac_int<32, true> temp;
-  ac_int<8, false> t8;
-  ac_int<1, true> bit;
-  ac_int<16, false> t16;
-
-  switch (opType) {
-    case STORE:
-      switch (mask) {
-        case BYTE_U:
-        case BYTE:
-          temp = data[addr >> 2];
-          data[addr >> 2].set_slc(((int)addr.slc<2>(0)) << 3, dataIn.slc<8>(0));
-          break;
-        case HALF:
-        case HALF_U:
-          temp = data[addr >> 2];
-          data[addr >> 2].set_slc(addr[1] ? 16 : 0, dataIn.slc<16>(0));
-
-          break;
-        case WORD:
-          temp            = data[addr >> 2];
-          data[addr >> 2] = dataIn;
-          break;
-      }
-      break;
-    case LOAD:
-      switch (mask) {
-        case BYTE:
-          t8  = data[addr >> 2].slc<8>(((int)addr.slc<2>(0)) << 3);
-          bit = t8.slc<1>(7);
-          dataOut.set_slc(0, t8);
-          dataOut.set_slc(8, (ac_int<24, true>)bit);
-          break;
-        case HALF:
-          t16 = data[addr >> 2].slc<16>(addr[1] ? 16 : 0);
-          bit = t16.slc<1>(15);
-          dataOut.set_slc(0, t16);
-          dataOut.set_slc(16, (ac_int<16, true>)bit);
-          break;
-        case WORD:
-          dataOut = data[addr >> 2];
-          break;
-        case BYTE_U:
-          dataOut = data[addr >> 2].slc<8>(((int)addr.slc<2>(0)) << 3) & 0xff;
-          break;
-        case HALF_U:
-          dataOut = data[addr >> 2].slc<16>(addr[1] ? 16 : 0) & 0xffff;
-          break;
-      }
-
-      break;
-  }
-  waitOut = false;
-}