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Commit 5e1bddd4 authored by Logan Fortune's avatar Logan Fortune

instruction and data Cache together HLS Passed

parent 12aa8167
Pipeline #206978 failed with stages
in 13 minutes and 43 seconds
......@@ -34,7 +34,7 @@ class CacheMemory : public MemoryInterface<INTERFACE_SIZE> {
static const int LOG_INTERFACE_SIZE = log2const<INTERFACE_SIZE>::value;
public:
MemoryInterface<INTERFACE_SIZE>* nextLevel;
IncompleteMemory<INTERFACE_SIZE>* nextLevel;
ac_int<TAG_SIZE + LINE_SIZE * 8, false> cacheMemory[SET_SIZE][ASSOCIATIVITY];
ac_int<40, false> age[SET_SIZE][ASSOCIATIVITY];
......@@ -66,7 +66,7 @@ public:
// Stats
unsigned long numberAccess, numberMiss;
CacheMemory(MemoryInterface<INTERFACE_SIZE>* nextLevel, bool v)
CacheMemory(IncompleteMemory<INTERFACE_SIZE>* nextLevel, bool v)
{
this->nextLevel = nextLevel;
for (int oneSetElement = 0; oneSetElement < SET_SIZE; oneSetElement++) {
......@@ -86,7 +86,7 @@ public:
}
void process(ac_int<32, false> addr, memMask mask, memOpType opType, ac_int<INTERFACE_SIZE * 8, false> dataIn,
ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut)
ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut, bool& releaseIDM)
{
// bit size is the log(setSize)
......@@ -107,7 +107,8 @@ public:
dataOut = dataOutStore;
wasStore = false;
cacheState = 0;
waitOut = 0;
return;
} else if (opType != NONE) {
ac_int<LINE_SIZE * 8 + TAG_SIZE, false> val1 = cacheMemory[place][0];
......@@ -354,8 +355,9 @@ public:
}
}
this->nextLevel->process(nextLevelAddr, LONG, nextLevelOpType, nextLevelDataIn, nextLevelDataOut, nextLevelWaitOut);
this->nextLevel->process(nextLevelAddr, LONG, nextLevelOpType, nextLevelDataIn, nextLevelDataOut, nextLevelWaitOut, nextLevelWaitOut);
waitOut = nextLevelWaitOut || cacheState || (wasStore && opType != NONE);
releaseIDM = nextLevelWaitOut || (cacheState != 0 && cacheState != 1);
}
};
......
......@@ -40,6 +40,7 @@ struct Core {
// stall
bool stallSignals[5] = {0, 0, 0, 0, 0};
bool stallIm, stallDm;
bool releaseIM, releaseDM;
unsigned long cycle;
/// Multicycle operation
......
......@@ -13,7 +13,7 @@ protected:
public:
virtual void process(ac_int<32, false> addr, memMask mask, memOpType opType, ac_int<INTERFACE_SIZE * 8, false> dataIn,
ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut) = 0;
ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut, bool& releaseIDM) = 0;
};
template <unsigned int INTERFACE_SIZE> class IncompleteMemory : public MemoryInterface<INTERFACE_SIZE> {
......@@ -23,7 +23,7 @@ public:
public:
IncompleteMemory(ac_int<32, false>* arg) { data = arg; }
void process(ac_int<32, false> addr, memMask mask, memOpType opType, ac_int<INTERFACE_SIZE * 8, false> dataIn,
ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut)
ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut, bool& releaseIDM)
{
// Incomplete memory only works for 32 bits
......@@ -31,6 +31,7 @@ public:
// no latency, wait is always set to false
waitOut = false;
releaseIDM = false;
if (opType == STORE) {
data[(addr >> 2) & 0xffffff] = dataIn;
} else if (opType == LOAD) {
......
This diff is collapsed.
......@@ -24,6 +24,20 @@ solution library add C28SOI_SC_12_CORE_LL_ccs -file /opt/DesignKit/catapult_lib/
go libraries
directive set -CLOCKS {clk {-CLOCK_PERIOD 2 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 1.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND sync -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_ACTIVE high}}
go assembly
directive set /doCore/core/imCache.cacheMemory:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/imCache.age:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/imCache.dataValid:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/dmCache.cacheMemory:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/dmCache.age:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/dmCache.dataValid:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/imCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/globalStall:rsc -MAP_TO_MODULE {[DirectInput]}
directive set /doCore/core/core.regFile:rsc -MAP_TO_MODULE {[Register]}
directive set /doCore/core/while -PIPELINE_INIT_INTERVAL 1
......
......@@ -23,11 +23,11 @@ BasicSimulator::BasicSimulator(std::string binaryFile, std::vector<std::string>
mem.reserve(DRAM_SIZE >> 2);
core.im = new SimpleMemory<4>(mem.data());
core.dm = new SimpleMemory<4>(mem.data());
//core.im = new SimpleMemory<4>(mem.data());
//core.dm = new SimpleMemory<4>(mem.data());
// core.im = new CacheMemory<4, 16, 64>(new SimpleMemory<4>(mem.data()), false);
// core.dm = new CacheMemory<4, 16, 64>(new SimpleMemory<4>(mem.data()), false);
core.im = new CacheMemory<4, 16, 64>(new IncompleteMemory<4>(mem.data()), false);
core.dm = new CacheMemory<4, 16, 64>(new IncompleteMemory<4>(mem.data()), false);
openFiles(inFile, outFile, tFile, sFile);
......@@ -167,8 +167,9 @@ void BasicSimulator::stb(ac_int<32, false> addr, ac_int<8, true> value)
{
ac_int<32, false> wordRes = 0;
bool stall = true;
bool releaseIDM = false;
while (stall)
core.dm->process(addr, BYTE, STORE, value, wordRes, stall);
core.dm->process(addr, BYTE, STORE, value, wordRes, stall, releaseIDM);
}
void BasicSimulator::sth(ac_int<32, false> addr, ac_int<16, true> value)
......@@ -203,8 +204,9 @@ ac_int<8, true> BasicSimulator::ldb(ac_int<32, false> addr)
result = mem[addr >> 2].slc<8>(((int)addr.slc<2>(0)) << 3);
ac_int<32, false> wordRes = 0;
bool stall = true;
bool releaseIDM = false;
while (stall)
core.dm->process(addr, BYTE_U, LOAD, 0, wordRes, stall);
core.dm->process(addr, BYTE_U, LOAD, 0, wordRes, stall, releaseIDM);
result = wordRes.slc<8>(0);
return result;
......
......@@ -516,6 +516,8 @@ void doCycle(struct Core& core, // Core containing all values
core.stallSignals[4] = 0;
core.stallIm = false;
core.stallDm = false;
core.releaseIM = false;
core.releaseDM = false;
// declare temporary structs
struct FtoDC ftoDC_temp;
......@@ -557,8 +559,7 @@ void doCycle(struct Core& core, // Core containing all values
// declare temporary register file
ac_int<32, false> nextInst;
if (!localStall && !core.stallDm)
core.im->process(core.pc, WORD, LOAD, 0, nextInst, core.stallIm);
core.im->process(core.pc, WORD, (!localStall && !core.releaseIM) ? LOAD : NONE, 0, nextInst, core.stallIm, core.releaseDM);
fetch(core.pc, ftoDC_temp, nextInst);
decode(core.ftoDC, dctoEx_temp, core.regFile);
......@@ -573,34 +574,35 @@ void doCycle(struct Core& core, // Core containing all values
memtoWB_temp.rd, memtoWB_temp.useRd, wbOut_temp.rd, wbOut_temp.useRd, core.stallSignals,
forwardRegisters);
if (!core.stallSignals[STALL_MEMORY] && !localStall && memtoWB_temp.we && !core.stallIm) {
memMask mask;
// TODO: carry the data size to memToWb
switch (core.extoMem.funct3) {
case 0:
mask = BYTE;
break;
case 1:
mask = HALF;
break;
case 2:
mask = WORD;
break;
case 4:
mask = BYTE_U;
break;
case 5:
mask = HALF_U;
break;
// Should NEVER happen
default:
mask = WORD;
break;
}
core.dm->process(memtoWB_temp.address, mask, memtoWB_temp.isLoad ? LOAD : (memtoWB_temp.isStore ? STORE : NONE),
memtoWB_temp.valueToWrite, memtoWB_temp.result, core.stallDm);
memMask mask;
// TODO: carry the data size to memToWb
switch (core.extoMem.funct3) {
case 0:
mask = BYTE;
break;
case 1:
mask = HALF;
break;
case 2:
mask = WORD;
break;
case 4:
mask = BYTE_U;
break;
case 5:
mask = HALF_U;
break;
// Should NEVER happen
default:
mask = WORD;
break;
}
memOpType opType = (!core.stallSignals[STALL_MEMORY] && !localStall && memtoWB_temp.we && !core.releaseDM && memtoWB_temp.isLoad) ? LOAD
: (!core.stallSignals[STALL_MEMORY] && !localStall && memtoWB_temp.we && !core.releaseDM && memtoWB_temp.isStore ? STORE : NONE);
core.dm->process(memtoWB_temp.address, mask, opType, memtoWB_temp.valueToWrite, memtoWB_temp.result, core.stallDm, core.releaseIM);
// commit the changes to the pipeline register
if (!core.stallSignals[STALL_FETCH] && !localStall && !core.stallIm && !core.stallDm) {
core.ftoDC = ftoDC_temp;
......@@ -666,10 +668,11 @@ void doCore(bool globalStall, ac_int<32, false> imData[1 << 24], ac_int<32, fals
IncompleteMemory<4> imInterface = IncompleteMemory<4>(imData);
IncompleteMemory<4> dmInterface = IncompleteMemory<4>(dmData);
// CacheMemory<4, 16, 64> dmCache = CacheMemory<4, 16, 64>(&dmInterface, false);
CacheMemory<4, 16, 64> dmCache = CacheMemory<4, 16, 64>(&dmInterface, false);
CacheMemory<4, 16, 64> imCache = CacheMemory<4, 16, 64>(&imInterface, false);
core.im = &imInterface;
core.dm = &dmInterface;
core.im = &imCache;
core.dm = &dmCache;
core.pc = 0;
while (1) {
......
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