Commit 4dbfde8e authored by LAVIGNE Mathis's avatar LAVIGNE Mathis
Browse files

Disabling interrupts when triggering an exception

parent e5e65434
Pipeline #271512 failed with stages
in 1 minute and 33 seconds
......@@ -385,6 +385,10 @@ public:
case RISCV_SYSTEM_ENV_ECALL:
// ECALL jumps to the IRQ handler code, whose adress is stored in mtvec lower bits
this->mepc = dctoEx.pc;
this->mstatus[7] = this->mstatus[3];
// this->mstatus[3] = 0;
// this->mstatus[11] = 1; // MPP 1
// this->mstatus[12] = 1; // MPP 2
this->mcause = 11; // environment call from machine mode 0x00000 -> exception
result_reg = mtvec;
setPC_reg = true & HAS_KERNEL_SYSCALL_HANDLER;
......@@ -396,7 +400,8 @@ public:
// We change interrupt enable bits (MIE = MPIE and MPIE = 1)
//if (!stall_cpu) {
this->mstatus[3] = this->mstatus[7];
this->mstatus[7] = 1;
this->mstatus[7] = 0;
break;
case RISCV_SYSTEM_ENV_EBREAK:
this->mepc = dctoEx.pc;
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment