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Commit 2c68e71e authored by ROKICKI Simon's avatar ROKICKI Simon

Change script and increase memory adress size in generated HW

parent eb97ee10
Pipeline #129158 failed with stages
in 3 minutes and 25 seconds
......@@ -32,9 +32,9 @@ public:
// no latency, wait is always set to false
waitOut = false;
if (opType == STORE) {
data[addr >> 2] = dataIn;
data[(addr >> 2) & 0xffffff] = dataIn;
} else if (opType == LOAD) {
dataOut = data[addr >> 2];
dataOut = data[(addr >> 2) & 0xffffff];
}
}
};
......
......@@ -29,5 +29,6 @@ directive set /doCore/imData:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_NOCHANGE
directive set /doCore/dmData:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_NOCHANGE
directive set /doCore/core/core.regFile:rsc -MAP_TO_MODULE {[Register]}
directive set /doCore/core/while -PIPELINE_INIT_INTERVAL 1
directive set /doCore/core/core.multiplicationUnit.process:if:else:for -UNROLL yes
go architect
go extract
......@@ -740,7 +740,7 @@ void doCycle(struct Core& core, // Core containing all values
}
// void doCore(IncompleteMemory im, IncompleteMemory dm, bool globalStall)
void doCore(bool globalStall, ac_int<32, false> imData[8192], ac_int<32, false> dmData[8192])
void doCore(bool globalStall, ac_int<32, false> imData[1 << 24], ac_int<32, false> dmData[1 << 24])
{
Core core;
IncompleteMemory<4> imInterface = IncompleteMemory<4>(imData);
......
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