Commit 294f73ec authored by logan's avatar logan
Browse files

better arch

parent 06ce9f00
Pipeline #272294 failed with stages
in 2 minutes and 49 seconds
......@@ -191,7 +191,7 @@ void CacheMemoryL2<INTERFACE_SIZE, LINE_SIZE, SET_SIZE>::processL2(cacheL2Direct
{
ac_int<32, false> addr = bufferIn.addr;
memMask mask = bufferIn.mask;
memMask mask = LONG;
memOpType opType = bufferIn.interfaceRequest;
ac_int<INTERFACE_SIZE * 8, false> dataIn = bufferIn.buffer;
ac_int<4, false> hartid = bufferIn.hartid;
......
......@@ -104,7 +104,6 @@ public:
memOpType nextLevelOpType;
ac_int<INTERFACE_SIZE * 8, false> nextLevelDataIn;
ac_int<INTERFACE_SIZE * 8, false> nextLevelDataOut;
memMask nextLevelMask;
ac_int<40, false> cycle;
ac_int<LOG_ASSOCIATIVITY, false> setMiss;
......@@ -307,7 +306,6 @@ public:
nextLevelAddr = addr;
nextLevelOpType = opType;
nextLevelDataIn = dataIn;
nextLevelMask = mask;
cacheState = 2; // avoid the first "if" statement
//printf("**L1 %d CLINT %x %c **\n",(unsigned int) hartid, (unsigned int)addr>>2, (unsigned int)dataIn);
} else if (cacheState == 2 && addrSuperior && addrInferior && !enter_directory_request) {
......@@ -552,7 +550,6 @@ public:
nextLevelAddr = (((int)addr.slc<32 - LOG_LINE_SIZE>(LOG_LINE_SIZE)) << LOG_LINE_SIZE) +
((cacheState - STATE_CACHE_LAST_LOAD - 1) << LOG_INTERFACE_SIZE);
nextLevelOpType = LOAD;//(cacheState == STATE_CACHE_FIRST_LOAD) ? DATA_FIRST_ACQ : DATA_ACQ;
nextLevelMask = LONG;
}
}
......@@ -631,7 +628,7 @@ public:
}
} // opType != NONE
} //! nextLevelWaitOut
this->nextLevel->process(nextLevelAddr, nextLevelMask, nextLevelOpType, hartid, nextLevelDataIn, nextLevelDataOut, nextLevelWaitOut, directoryRequestStall);
this->nextLevel->process(nextLevelAddr, LONG, nextLevelOpType, hartid, nextLevelDataIn, nextLevelDataOut, nextLevelWaitOut, directoryRequestStall);
waitOut = (nextLevelWaitOut && opType != NONE) || cacheState || wasStore || amoDataReq ||
(this->nextLevel->bufferIn->interfaceAck && opType != NONE && !missDone);
}
......
......@@ -53,13 +53,13 @@ struct cacheDirectoryInterfaceBase {
ac_int<32, false> addr;
ac_int<1, false> interfaceAck;
ac_int<1, false> releaseAck;
memMask mask;
// data_req
ac_int<32, false> buffer;
};
typedef struct cacheDirectoryInterfaceOut : public cacheDirectoryInterfaceBase {
memOpType interfaceRequest;
// data out
ac_int<32, false> buffer;
// data In
ac_int<32, false> bufferIn;
} cacheDirectoryInterfaceOut;
......@@ -70,6 +70,8 @@ typedef struct cacheDirectoryInterfaceIn : public cacheDirectoryInterfaceBase {
// cache L2
typedef struct cacheL2DirectoryInterfaceOut : public cacheDirectoryInterfaceBase {
// data out
ac_int<32, false> buffer;
ac_int<1, false> protocolMiss;
directoryOpType interfaceRequest;
ac_int<4, false> hartid;
......@@ -89,6 +91,8 @@ typedef struct cacheL2DirectoryInterfaceIn : public cacheDirectoryInterfaceBase
ac_int<1, false> interfaceAckWB;
ac_int<1, false> releaseAckWB;
ac_int<32, false> addrWB;
// data in
ac_int<32, false> buffer;
ac_int<32, false> bufferWB;
} cacheL2DirectoryInterfaceIn;
......@@ -300,7 +304,6 @@ public:
bufferOutWB->interfaceAck = 1;
bufferOutWB->interfaceRequest = opType;
bufferOutWB->buffer = dataIn;
bufferOutWB->mask = mask;
stateDirectoryRequest = true;
//printf("//Directory Bus Asking...\n");
} else {
......@@ -321,7 +324,6 @@ public:
bufferOut->interfaceAck = 1;
bufferOut->interfaceRequest = opType;
bufferOut->buffer = dataIn;
bufferOut->mask = mask;
waitOut = true;
this->wait = waitOut;
printIO = true;
......@@ -358,7 +360,6 @@ public:
bufferOut->interfaceAck = 1;
bufferOut->interfaceRequest = opType;
bufferOut->buffer = dataIn;
bufferOut->mask = mask;
waitOut = true;
this->wait = waitOut;
//printf("//Request to the directory... %x %x %d\n", bufferOut->addr, opType,
......
......@@ -43,8 +43,6 @@ BasicSimulator::BasicSimulator(std::string binaryFile,
interfaceOut[i][2].releaseAck = 0;
interfaceOut[i][3].releaseAck = 0;
interfaceIn[i][0].buffer = 0;
interfaceIn[i][1].buffer = 0;
interfaceOut[i][0].buffer = 0;
interfaceOut[i][1].buffer = 0;
interfaceOut[i][0].bufferIn = 0;
......
......@@ -236,7 +236,7 @@ void doDirectory(std::vector<ac_int<32, false> >& mem, const int nb_cores, bool
if (bufferOut[i][j].interfaceRequest == STORE) { // CLINT-UART
ac_int<32, false> dataOut_temp = 0;
memoryStoreLoad(p_mem, bufferOut[i][j].addr, bufferOut[i][j].mask, bufferOut[i][j].interfaceRequest,
memoryStoreLoad(p_mem, bufferOut[i][j].addr, LONG, bufferOut[i][j].interfaceRequest,
bufferOut[i][j].buffer, dataOut_temp, cacheWait);
bufferOut[i][j].releaseAck = cacheWait;
//printf("Verif Store : %x @(%x)\n", p_mem[0x40], (bufferOut[i][j].addr>>2) & MEMMASK);
......@@ -245,14 +245,14 @@ void doDirectory(std::vector<ac_int<32, false> >& mem, const int nb_cores, bool
// cache L2 call
ac_int<32, false> dataIn_temp = 0;
bufferOut[i][j].bufferIn = 0;
memoryStoreLoad(p_mem, bufferOut[i][j].addr, bufferOut[i][j].mask, bufferOut[i][j].interfaceRequest,
memoryStoreLoad(p_mem, bufferOut[i][j].addr, LONG, bufferOut[i][j].interfaceRequest,
dataIn_temp, bufferOut[i][j].bufferIn , cacheWait);
bufferOut[i][j].releaseAck = cacheWait;
//printf("%d %d ACQ/LOAD: %x %x\n", i, j, bufferOut[i][j].addr, bufferOut[i][j].bufferIn );
} else if (bufferOut[i][j].interfaceRequest == AMO_SC) {
if (reservationAMO[i].valid && reservationAMO[i].address == bufferOut[i][j].addr) {
ac_int<32, false> dataOut_temp = 0;
memoryStoreLoad(p_mem, bufferOut[i][j].addr, bufferOut[i][j].mask, STORE, bufferOut[i][j].buffer,
memoryStoreLoad(p_mem, bufferOut[i][j].addr, LONG, STORE, bufferOut[i][j].buffer,
dataOut_temp, cacheWait); // not optimized --> should know whether it is in cache or not !
bufferOut[i][j].releaseAck = cacheWait;
if(cacheWait)
......
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