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memoryInterface.h 4.29 KB
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/** Copyright 2021 INRIA, Université de Rennes 1 and ENS Rennes
*
*   Licensed under the Apache License, Version 2.0 (the "License");
*   you may not use this file except in compliance with the License.
*   You may obtain a copy of the License at
*       http://www.apache.org/licenses/LICENSE-2.0
*   Unless required by applicable law or agreed to in writing, software
*   distributed under the License is distributed on an "AS IS" BASIS,
*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*   See the License for the specific language governing permissions and
*   limitations under the License.
*/



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#ifndef __MEMORY_INTERFACE_H__
#define __MEMORY_INTERFACE_H__

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#include "ac_int.h"
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typedef enum { BYTE = 0, HALF, WORD, BYTE_U, HALF_U, LONG } memMask;
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typedef enum { NONE = 0, LOAD, STORE } memOpType;
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template <unsigned int INTERFACE_SIZE> class MemoryInterface {
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protected:
  bool wait;

public:
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  virtual void process(const ac_int<32, false> addr, const memMask mask, const memOpType opType, const ac_int<INTERFACE_SIZE * 8, false> dataIn,
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                       ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut) = 0;
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};

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template <unsigned int INTERFACE_SIZE> class IncompleteMemory : public MemoryInterface<INTERFACE_SIZE> {
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public:
  ac_int<32, false>* data;

public:
  IncompleteMemory(ac_int<32, false>* arg) { data = arg; }
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  void process(const ac_int<32, false> addr, const memMask mask, const memOpType opType, const ac_int<INTERFACE_SIZE * 8, false> dataIn,
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               ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut)
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  {
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    // Incomplete memory only works for 32 bits
    assert(INTERFACE_SIZE == 4);

    // no latency, wait is always set to false
    waitOut = false;
    if (opType == STORE) {
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      data[(addr >> 2) & 0xffffff] = dataIn;
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    } else if (opType == LOAD) {
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      dataOut = data[(addr >> 2) & 0xffffff];
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    }
  }
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};

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template <unsigned int INTERFACE_SIZE> class SimpleMemory : public MemoryInterface<INTERFACE_SIZE> {
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public:
  ac_int<32, false>* data;

  SimpleMemory(ac_int<32, false>* arg) { data = arg; }
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  void process(const ac_int<32, false> addr, const memMask mask, const memOpType opType, const ac_int<INTERFACE_SIZE * 8, false> dataIn,
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               ac_int<INTERFACE_SIZE * 8, false>& dataOut, bool& waitOut)
  {
    // no latency, wait is always set to false

    ac_int<32, true> temp;
    ac_int<8, false> t8;
    ac_int<1, true> bit;
    ac_int<16, false> t16;

    switch (opType) {
      case STORE:
        switch (mask) {
          case BYTE_U:
          case BYTE:
            temp = data[addr >> 2];
            data[addr >> 2].set_slc(((int)addr.slc<2>(0)) << 3, dataIn.template slc<8>(0));
            break;
          case HALF:
          case HALF_U:
            temp = data[addr >> 2];
            data[addr >> 2].set_slc(addr[1] ? 16 : 0, dataIn.template slc<16>(0));
            break;
          case WORD:
            temp            = data[addr >> 2];
            data[addr >> 2] = dataIn;
            break;
          case LONG:
            for (int oneWord = 0; oneWord < INTERFACE_SIZE / 4; oneWord++)
              data[(addr >> 2) + oneWord] = dataIn.template slc<32>(32 * oneWord);
            break;
        }
        break;
      case LOAD:
        switch (mask) {
          case BYTE:
            t8  = data[addr >> 2].slc<8>(((int)addr.slc<2>(0)) << 3);
            bit = t8.slc<1>(7);
            dataOut.set_slc(0, t8);
            dataOut.set_slc(8, (ac_int<24, true>)bit);
            break;
          case HALF:
            t16 = data[addr >> 2].slc<16>(addr[1] ? 16 : 0);
            bit = t16.slc<1>(15);
            dataOut.set_slc(0, t16);
            dataOut.set_slc(16, (ac_int<16, true>)bit);
            break;
          case WORD:
            dataOut = data[addr >> 2];
            break;
          case LONG:
            for (int oneWord = 0; oneWord < INTERFACE_SIZE / 4; oneWord++)
              dataOut.set_slc(32 * oneWord, data[(addr >> 2) + oneWord]);
            break;
          case BYTE_U:
            dataOut = data[addr >> 2].slc<8>(((int)addr.slc<2>(0)) << 3) & 0xff;
            break;
          case HALF_U:
            dataOut = data[addr >> 2].slc<16>(addr[1] ? 16 : 0) & 0xffff;
            break;
        }
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        break;
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      default: // case NONE
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        break;
    }
    waitOut = false;
  }
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};

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#endif //__MEMORY_INTERFACE_H__