diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/dgemm.mirage b/simucore/perfmodels/.starpu/sampling/codelets/45/dgemm.mirage new file mode 100644 index 0000000000000000000000000000000000000000..dad23a16172e673374e9c8f48f688b6b9161c141 --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/dgemm.mirage @@ -0,0 +1,152 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +4 +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb3_impl0: cpu +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +20a74a79 2252800 0.000000e+00 5.714967e+03 9.983302e+01 1.861365e+07 1.064089e+11 3257 +d46431bb 2457600 0.000000e+00 6.572893e+03 9.671459e+02 1.516432e+08 1.018314e+12 23071 +24c84a50 22118400 0.000000e+00 1.729324e+05 2.099315e+03 4.762558e+08 8.237217e+13 2754 +94526596 14131200 0.000000e+00 8.066041e+04 2.228611e+03 3.461945e+08 2.794551e+13 4292 +d041c8f5 1228800 0.000000e+00 1.783073e+03 6.303677e+02 1.489757e+07 2.988342e+10 8355 + +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb0_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +20a74a79 2252800 0.000000e+00 3.095456e+02 2.053203e+02 7.525053e+05 3.354169e+08 2431 +d46431bb 2457600 0.000000e+00 3.270395e+02 2.436610e+02 2.585346e+07 1.314853e+10 79053 +24c84a50 22118400 0.000000e+00 5.981205e+03 3.102152e+02 1.503555e+08 9.017264e+11 25138 +94526596 14131200 0.000000e+00 2.881518e+03 4.199780e+02 2.276399e+06 6.698827e+09 790 +d041c8f5 1228800 0.000000e+00 2.338286e+02 1.144770e+02 6.921326e+04 2.006311e+07 296 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb1_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +20a74a79 2252800 0.000000e+00 3.016439e+02 4.389580e+01 8.949776e+05 2.756815e+08 2967 +d46431bb 2457600 0.000000e+00 3.302564e+02 3.287456e+02 2.582341e+07 1.697884e+10 78192 +24c84a50 22118400 0.000000e+00 5.971525e+03 2.301128e+02 1.521067e+08 9.096577e+11 25472 +94526596 14131200 0.000000e+00 2.861859e+03 8.311454e+01 2.632911e+06 7.541376e+09 920 +d041c8f5 1228800 0.000000e+00 2.238745e+02 1.263761e+02 6.850561e+04 2.022376e+07 306 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb2_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +20a74a79 2252800 0.000000e+00 3.197659e+02 1.633721e+02 8.716819e+05 3.514923e+08 2726 +d46431bb 2457600 0.000000e+00 3.408506e+02 3.203963e+02 2.609552e+07 1.675385e+10 76560 +24c84a50 22118400 0.000000e+00 5.988062e+03 3.050672e+02 1.507315e+08 9.049323e+11 25172 +94526596 14131200 0.000000e+00 2.850260e+03 5.292387e+01 2.633640e+06 7.509149e+09 924 +d041c8f5 1228800 0.000000e+00 2.356252e+02 1.206585e+02 7.987695e+04 2.375635e+07 339 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/dgemm.sirocco b/simucore/perfmodels/.starpu/sampling/codelets/45/dgemm.sirocco new file mode 100644 index 0000000000000000000000000000000000000000..1367c8e02a93d9998c4ee9f3ff76bad9882289f3 --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/dgemm.sirocco @@ -0,0 +1,188 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +5 +#################### +# COMB_4 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cpu0_impl0 (Comb4) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +24c84a50 22118400 0.000000e+00 7.614739e+04 1.570335e+04 4.926736e+07 3.911128e+12 647 +e6b94418 153600 0.000000e+00 5.080183e+01 9.743801e+00 2.861616e+06 1.507233e+08 56329 +c4a08f5f 4646400 0.000000e+00 8.137654e+03 1.863872e+03 1.657640e+07 1.419696e+11 2037 +8cfc3ba0 49766400 0.000000e+00 2.267816e+05 3.915016e+04 1.598810e+08 3.733864e+13 705 +a7cdf15b 88473600 0.000000e+00 4.662963e+05 5.310256e+04 3.273400e+08 1.546170e+14 702 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda1_impl0 (Comb1) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +24c84a50 22118400 0.000000e+00 1.715310e+03 9.993558e+01 9.566285e+06 1.646484e+10 5577 +e6b94418 153600 0.000000e+00 5.113274e+01 1.134809e+01 1.518642e+04 8.147708e+05 297 +c4a08f5f 4646400 0.000000e+00 2.017727e+02 2.861061e+01 1.652922e+06 3.402201e+08 8192 +8cfc3ba0 49766400 0.000000e+00 6.191028e+03 2.666186e+02 2.317302e+07 1.437309e+11 3743 +a7cdf15b 88473600 0.000000e+00 1.292684e+04 4.908603e+02 4.657542e+07 6.029413e+11 3603 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda0_impl0 (Comb2) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +24c84a50 22118400 0.000000e+00 1.694044e+03 9.446026e+01 9.451069e+06 1.606030e+10 5579 +e6b94418 153600 0.000000e+00 6.271543e+01 1.282513e+01 1.994351e+04 1.303072e+06 318 +c4a08f5f 4646400 0.000000e+00 2.001219e+02 2.795923e+01 1.640199e+06 3.346467e+08 8196 +8cfc3ba0 49766400 0.000000e+00 6.117615e+03 2.941760e+02 2.339376e+07 1.434449e+11 3824 +a7cdf15b 88473600 0.000000e+00 1.279991e+04 4.666369e+02 4.609249e+07 5.907639e+11 3601 + +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda2_impl0 (Comb0) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +24c84a50 22118400 0.000000e+00 1.713334e+03 9.294880e+01 9.365083e+06 1.609274e+10 5466 +e6b94418 153600 0.000000e+00 4.994209e+01 9.498420e+00 1.588158e+04 8.218495e+05 318 +c4a08f5f 4646400 0.000000e+00 2.026661e+02 2.758349e+01 1.561340e+06 3.222922e+08 7704 +8cfc3ba0 49766400 0.000000e+00 6.177427e+03 2.260170e+02 2.327037e+07 1.439434e+11 3767 +a7cdf15b 88473600 0.000000e+00 1.286952e+04 4.739314e+02 4.932886e+07 6.356995e+11 3833 + +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +3 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda3_impl0 (Comb3) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +24c84a50 22118400 0.000000e+00 1.680328e+03 1.055142e+02 9.028404e+06 1.523050e+10 5373 +e6b94418 153600 0.000000e+00 5.000193e+01 1.025088e+01 7.350283e+03 3.829751e+05 147 +c4a08f5f 4646400 0.000000e+00 1.988673e+02 2.685130e+01 1.504233e+06 3.045963e+08 7564 +8cfc3ba0 49766400 0.000000e+00 6.051978e+03 2.759693e+02 2.305804e+07 1.398369e+11 3810 +a7cdf15b 88473600 0.000000e+00 1.258002e+04 4.620060e+02 4.874757e+07 6.140725e+11 3875 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/dplgsy.mirage b/simucore/perfmodels/.starpu/sampling/codelets/45/dplgsy.mirage new file mode 100644 index 0000000000000000000000000000000000000000..f0ca53d3c8ba9fb38736d4c64469a47d15962724 --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/dplgsy.mirage @@ -0,0 +1,49 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +1 +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb3_impl0: cpu +# number of entries +11 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +431274fd 627200 0.000000e+00 3.507212e+02 3.897980e+01 3.507212e+03 1.245248e+06 10 +4c6c92dc 716800 0.000000e+00 5.632527e+02 1.219837e+01 2.844426e+05 1.602882e+08 505 +c1dd9b4c 716800 0.000000e+00 8.750618e+02 5.882979e+02 4.419062e+05 5.614729e+08 505 +cea37d6d 819200 0.000000e+00 7.822003e+02 3.547361e+02 3.323960e+07 3.134750e+10 42495 +617e5fe6 7372800 0.000000e+00 9.115973e+03 3.699894e+03 1.299482e+08 1.379744e+12 14255 +471f3021 3379200 0.000000e+00 3.738489e+03 3.995652e+02 1.476703e+06 5.583702e+09 395 +be417c6f 3379200 0.000000e+00 2.589893e+03 3.021594e+01 1.023008e+06 2.649841e+09 395 +982013a8 1548800 0.000000e+00 7.591599e+02 8.959083e+00 7.591599e+03 5.764040e+06 10 +bec19f89 204800 0.000000e+00 2.385948e+02 3.416508e+01 1.476902e+05 3.596065e+07 619 +dd524d7f 204800 0.000000e+00 1.775137e+02 1.049637e+01 1.098810e+05 1.957358e+07 619 +ad30af9b 51200 0.000000e+00 3.296558e+01 1.621243e+00 6.263460e+02 2.069780e+04 19 diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/dplgsy.sirocco b/simucore/perfmodels/.starpu/sampling/codelets/45/dplgsy.sirocco new file mode 100644 index 0000000000000000000000000000000000000000..b827a8a50b9c11d18d389b195466eb95212d5783 --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/dplgsy.sirocco @@ -0,0 +1,44 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +1 +#################### +# COMB_4 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cpu0_impl0 (Comb4) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +617e5fe6 7372800 0.000000e+00 9.359014e+03 4.860060e+02 2.358472e+06 2.213249e+10 252 +ad30af9b 51200 0.000000e+00 9.876737e+01 1.343538e+01 1.590451e+06 1.599914e+08 16103 +982013a8 1548800 0.000000e+00 2.134161e+03 1.815312e+02 4.673812e+06 1.004683e+10 2190 +25ebb669 16588800 0.000000e+00 2.092160e+04 1.229935e+03 3.661280e+06 7.686456e+10 175 +5104f3b7 29491200 0.000000e+00 3.676615e+04 1.578675e+03 5.110494e+06 1.882396e+11 139 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/dpotrf.mirage b/simucore/perfmodels/.starpu/sampling/codelets/45/dpotrf.mirage new file mode 100644 index 0000000000000000000000000000000000000000..715769a70c3c8d3c3cb5d2136ae7ccf51f3ff1e9 --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/dpotrf.mirage @@ -0,0 +1,144 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +4 +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb3_impl0: cpu +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +431274fd 627200 0.000000e+00 1.030682e+03 4.474767e+00 1.030682e+04 1.062325e+07 10 +cea37d6d 819200 0.000000e+00 1.622851e+03 7.237150e+02 1.772153e+06 3.447889e+09 1092 +617e5fe6 7372800 0.000000e+00 3.362389e+04 1.714866e+03 1.028891e+07 3.468531e+11 306 +982013a8 1548800 0.000000e+00 3.571803e+03 3.350912e+01 3.571803e+04 1.275890e+08 10 +ad30af9b 51200 0.000000e+00 5.419050e+01 1.086799e+01 5.419050e+02 3.054724e+04 10 + +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb0_impl0: cuda +# number of entries +3 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +ad30af9b 51200 0.000000e+00 1.498917e+03 2.849950e+01 1.199133e+04 1.798051e+07 8 +cea37d6d 819200 0.000000e+00 3.668830e+03 8.172072e+02 3.668830e+04 1.412814e+08 10 +617e5fe6 7372800 0.000000e+00 1.204932e+04 4.628557e+03 6.024659e+05 8.330481e+09 50 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb1_impl0: cuda +# number of entries +2 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +cea37d6d 819200 0.000000e+00 3.541486e+03 3.172789e+02 3.541486e+04 1.264279e+08 10 +617e5fe6 7372800 0.000000e+00 3.066868e+04 1.574010e+04 3.680241e+05 1.425982e+10 12 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb2_impl0: cuda +# number of entries +2 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +cea37d6d 819200 0.000000e+00 3.230490e+03 3.627237e+02 3.230490e+04 1.056763e+08 10 +617e5fe6 7372800 0.000000e+00 2.054158e+04 1.124016e+04 4.929979e+05 1.315915e+10 24 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/dpotrf.sirocco b/simucore/perfmodels/.starpu/sampling/codelets/45/dpotrf.sirocco new file mode 100644 index 0000000000000000000000000000000000000000..417dacac436cc4369807f21dab429b71717b7abe --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/dpotrf.sirocco @@ -0,0 +1,188 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +5 +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda0_impl0 (Comb1) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +25ebb669 16588800 0.000000e+00 1.927652e+04 3.502107e+03 9.059964e+05 1.804090e+10 47 +617e5fe6 7372800 0.000000e+00 1.229853e+04 1.768810e+03 6.149267e+05 7.719131e+09 50 +ad30af9b 51200 0.000000e+00 2.101636e+03 2.756395e+02 1.303014e+05 2.785568e+08 62 +982013a8 1548800 0.000000e+00 4.903930e+03 3.193701e+02 2.550044e+05 1.255828e+09 52 +5104f3b7 29491200 0.000000e+00 2.463348e+04 2.985247e+03 1.576542e+06 3.940607e+10 64 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda2_impl0 (Comb2) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +25ebb669 16588800 0.000000e+00 1.940135e+04 4.068762e+03 6.984485e+05 1.414682e+10 36 +617e5fe6 7372800 0.000000e+00 1.194505e+04 1.978674e+03 3.822416e+05 4.691180e+09 32 +ad30af9b 51200 0.000000e+00 2.114340e+03 2.957222e+02 1.268604e+05 2.734732e+08 60 +982013a8 1548800 0.000000e+00 5.046035e+03 5.465455e+02 1.766112e+05 9.016412e+08 35 +5104f3b7 29491200 0.000000e+00 2.329330e+04 2.356823e+03 1.094785e+06 2.576222e+10 47 + +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +3 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda3_impl0 (Comb3) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +25ebb669 16588800 0.000000e+00 1.848606e+04 2.220768e+03 5.545817e+05 1.039998e+10 30 +617e5fe6 7372800 0.000000e+00 1.174012e+04 1.793250e+03 3.991641e+05 4.795570e+09 34 +ad30af9b 51200 0.000000e+00 2.130842e+03 3.337398e+02 1.576823e+05 3.442383e+08 74 +982013a8 1548800 0.000000e+00 5.078755e+03 5.140761e+02 2.437802e+05 1.250785e+09 48 +5104f3b7 29491200 0.000000e+00 2.451908e+04 3.131104e+03 5.884580e+05 1.466374e+10 24 + +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda1_impl0 (Comb0) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +25ebb669 16588800 0.000000e+00 1.807832e+04 2.125912e+03 7.412111e+05 1.358515e+10 41 +ad30af9b 51200 0.000000e+00 2.127387e+03 2.904710e+02 1.404075e+05 3.042697e+08 66 +617e5fe6 7372800 0.000000e+00 1.177248e+04 1.259016e+03 4.002642e+05 4.765995e+09 34 +982013a8 1548800 0.000000e+00 4.993474e+03 5.010162e+02 2.546672e+05 1.284476e+09 51 +5104f3b7 29491200 0.000000e+00 2.412058e+04 2.891586e+03 1.206029e+06 2.950819e+10 50 + +#################### +# COMB_4 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cpu0_impl0 (Comb4) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +25ebb669 16588800 0.000000e+00 3.521786e+04 3.719259e+03 2.183508e+06 7.775611e+10 62 +982013a8 1548800 0.000000e+00 1.965233e+03 3.623952e+02 7.271360e+04 1.477584e+08 37 +617e5fe6 7372800 0.000000e+00 1.125962e+04 1.634952e+03 5.855000e+05 6.731505e+09 52 +ad30af9b 51200 0.000000e+00 4.077398e+01 4.776338e+00 2.487213e+03 1.028052e+05 61 +5104f3b7 29491200 0.000000e+00 7.956441e+04 8.548094e+03 5.410380e+06 4.354424e+11 68 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/dsyrk.mirage b/simucore/perfmodels/.starpu/sampling/codelets/45/dsyrk.mirage new file mode 100644 index 0000000000000000000000000000000000000000..a1c91456d87d007e8232a45a1c9d3a489eebe2cd --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/dsyrk.mirage @@ -0,0 +1,152 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +4 +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb3_impl0: cpu +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +5a15b6c4 1344000 0.000000e+00 3.023275e+03 7.746548e+01 1.136751e+06 3.438968e+09 376 +2c1922b7 1638400 0.000000e+00 3.932783e+03 6.671761e+02 6.229528e+07 2.520446e+11 15840 +ff82dda0 14745600 0.000000e+00 9.688974e+04 2.617919e+03 3.706032e+08 3.593387e+13 3825 +9027d1ef 4928000 0.000000e+00 2.115389e+04 1.076983e+03 6.303861e+06 1.336969e+11 298 +3bcdebeb 256000 0.000000e+00 3.186986e+02 1.977274e+01 1.864387e+05 5.964644e+07 585 + +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb0_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +5a15b6c4 1344000 0.000000e+00 3.115819e+02 4.187818e+01 1.184011e+04 3.755808e+06 38 +2c1922b7 1638400 0.000000e+00 3.389968e+02 7.785639e+01 5.051053e+05 1.802609e+08 1490 +ff82dda0 14745600 0.000000e+00 3.706104e+03 1.590827e+02 4.102658e+06 1.523289e+10 1107 +9027d1ef 4928000 0.000000e+00 1.273837e+03 2.694431e+02 5.732266e+04 7.628671e+07 45 +3bcdebeb 256000 0.000000e+00 8.116750e+01 5.964729e+00 8.116750e+02 6.623741e+04 10 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb1_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +5a15b6c4 1344000 0.000000e+00 3.115786e+02 4.014208e+01 1.402103e+04 4.441166e+06 45 +2c1922b7 1638400 0.000000e+00 3.454345e+02 8.849317e+01 6.062375e+05 2.231588e+08 1755 +ff82dda0 14745600 0.000000e+00 3.689895e+03 1.766143e+02 3.800592e+06 1.405591e+10 1030 +9027d1ef 4928000 0.000000e+00 1.304116e+03 2.231084e+02 3.129879e+04 4.201193e+07 24 +3bcdebeb 256000 0.000000e+00 1.083755e+02 7.138430e+00 1.083755e+03 1.179621e+05 10 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb2_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +5a15b6c4 1344000 0.000000e+00 3.112067e+02 2.934804e+01 1.338189e+04 4.201569e+06 43 +2c1922b7 1638400 0.000000e+00 3.521904e+02 1.864128e+02 5.620958e+05 2.534253e+08 1596 +ff82dda0 14745600 0.000000e+00 3.688518e+03 1.323982e+02 3.555731e+06 1.313228e+10 964 +9027d1ef 4928000 0.000000e+00 1.257845e+03 9.056672e+01 3.144613e+04 3.975942e+07 25 +3bcdebeb 256000 0.000000e+00 1.501611e+02 1.222134e+02 1.651772e+03 4.123292e+05 11 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/dsyrk.sirocco b/simucore/perfmodels/.starpu/sampling/codelets/45/dsyrk.sirocco new file mode 100644 index 0000000000000000000000000000000000000000..5f66280efdb356e7a696f784b768fca3e3d44381 --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/dsyrk.sirocco @@ -0,0 +1,188 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +5 +#################### +# COMB_4 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cpu0_impl0 (Comb4) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +ff82dda0 14745600 0.000000e+00 3.671926e+04 6.264954e+03 4.868973e+07 1.839896e+12 1326 +5831f4e0 102400 0.000000e+00 3.685897e+01 6.246340e+00 2.291522e+05 8.688881e+06 6217 +6a2f38af 3097600 0.000000e+00 3.808134e+03 7.661841e+02 8.320772e+06 3.296929e+10 2185 +0e8bce2b 33177600 0.000000e+00 1.197936e+05 2.202875e+04 9.260042e+07 1.146804e+13 773 +f001bd15 58982400 0.000000e+00 2.500810e+05 3.400228e+04 1.668040e+08 4.248568e+13 667 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda0_impl0 (Comb2) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +ff82dda0 14745600 0.000000e+00 1.225366e+03 1.055960e+02 2.940879e+05 3.630415e+08 240 +5831f4e0 102400 0.000000e+00 6.983900e+01 1.260925e+01 8.380680e+02 6.043775e+04 12 +6a2f38af 3097600 0.000000e+00 2.036579e+02 2.324388e+01 5.885713e+04 1.214286e+07 289 +0e8bce2b 33177600 0.000000e+00 3.666675e+03 2.800845e+02 7.150015e+05 2.636975e+09 195 +f001bd15 58982400 0.000000e+00 7.329175e+03 4.915258e+02 1.693039e+06 1.246439e+10 231 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda1_impl0 (Comb1) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +ff82dda0 14745600 0.000000e+00 1.251704e+03 9.523925e+01 2.928988e+05 3.687452e+08 234 +5831f4e0 102400 0.000000e+00 7.712755e+01 1.662959e+01 8.484030e+02 6.847722e+04 11 +6a2f38af 3097600 0.000000e+00 2.078053e+02 2.202377e+01 5.402939e+04 1.135371e+07 260 +0e8bce2b 33177600 0.000000e+00 3.720059e+03 2.853133e+02 8.295732e+05 3.104214e+09 223 +f001bd15 58982400 0.000000e+00 7.383529e+03 3.772204e+02 1.580075e+06 1.169698e+10 214 + +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda2_impl0 (Comb0) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +ff82dda0 14745600 0.000000e+00 1.252296e+03 1.169465e+02 2.955417e+05 3.733333e+08 236 +5831f4e0 102400 0.000000e+00 7.692512e+01 1.259036e+01 1.230802e+03 9.721587e+04 16 +6a2f38af 3097600 0.000000e+00 2.079242e+02 2.471557e+01 6.029802e+04 1.271457e+07 290 +0e8bce2b 33177600 0.000000e+00 3.744678e+03 3.676926e+02 7.938716e+05 3.001455e+09 212 +f001bd15 58982400 0.000000e+00 7.454402e+03 4.686588e+02 1.669786e+06 1.249646e+10 224 + +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +3 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda3_impl0 (Comb3) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +ff82dda0 14745600 0.000000e+00 1.227027e+03 1.116503e+02 2.908055e+05 3.597807e+08 237 +5831f4e0 102400 0.000000e+00 7.100592e+01 1.678181e+01 8.520710e+02 6.388163e+04 12 +6a2f38af 3097600 0.000000e+00 2.027211e+02 2.465123e+01 5.331564e+04 1.096802e+07 263 +0e8bce2b 33177600 0.000000e+00 3.582949e+03 2.599939e+02 6.341819e+05 2.284206e+09 177 +f001bd15 58982400 0.000000e+00 7.239223e+03 4.831241e+02 1.360974e+06 9.896276e+09 188 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/dtrsm.mirage b/simucore/perfmodels/.starpu/sampling/codelets/45/dtrsm.mirage new file mode 100644 index 0000000000000000000000000000000000000000..5995a82ec1460c9d433e0360ba4cc52ea1936e65 --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/dtrsm.mirage @@ -0,0 +1,152 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +4 +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb3_impl0: cpu +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +2367c496 1536000 0.000000e+00 2.998203e+03 6.905988e+01 9.684196e+05 2.905059e+09 323 +2c1922b7 1638400 0.000000e+00 3.496929e+03 1.465878e+03 3.699051e+07 1.520832e+11 10578 +ff82dda0 14745600 0.000000e+00 8.919371e+04 2.100123e+03 1.820444e+08 1.624621e+13 2041 +d9e3b267 10752000 0.000000e+00 4.053189e+04 1.148917e+03 1.102467e+07 4.472099e+11 272 +5c7bc053 1024000 0.000000e+00 1.025142e+03 2.361696e+03 5.986828e+05 3.871057e+09 584 + +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb0_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +2367c496 1536000 0.000000e+00 8.363940e+02 1.125628e+02 3.429215e+04 2.920124e+07 41 +2c1922b7 1638400 0.000000e+00 7.559855e+02 2.183721e+02 2.596054e+06 2.126334e+09 3434 +ff82dda0 14745600 0.000000e+00 7.918084e+03 2.182130e+03 1.357160e+07 1.156226e+11 1714 +d9e3b267 10752000 0.000000e+00 4.642075e+03 8.340400e+01 2.831666e+05 1.314905e+09 61 +5c7bc053 1024000 0.000000e+00 5.394934e+02 3.448245e+01 5.934427e+03 3.214663e+06 11 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb1_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +2367c496 1536000 0.000000e+00 8.272168e+02 2.364402e+01 6.286847e+04 5.204834e+07 76 +2c1922b7 1638400 0.000000e+00 7.705068e+02 9.372148e+01 2.604313e+06 2.036330e+09 3380 +ff82dda0 14745600 0.000000e+00 7.897577e+03 2.452263e+03 1.198852e+07 1.038089e+11 1518 +d9e3b267 10752000 0.000000e+00 4.278092e+03 1.807577e+02 1.197866e+05 5.133728e+08 28 +5c7bc053 1024000 0.000000e+00 5.312194e+02 1.857079e+01 5.312194e+03 2.825389e+06 10 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb2_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +2367c496 1536000 0.000000e+00 8.889264e+02 2.402687e+01 5.511344e+04 4.902758e+07 62 +2c1922b7 1638400 0.000000e+00 7.538502e+02 1.001816e+02 2.479413e+06 1.902116e+09 3289 +ff82dda0 14745600 0.000000e+00 7.947228e+03 4.525425e+02 1.313677e+07 1.047394e+11 1653 +d9e3b267 10752000 0.000000e+00 4.733316e+03 1.294680e+02 1.467328e+05 6.950524e+08 31 +5c7bc053 1024000 0.000000e+00 5.947083e+02 1.879919e+02 6.541791e+03 4.279208e+06 11 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/dtrsm.sirocco b/simucore/perfmodels/.starpu/sampling/codelets/45/dtrsm.sirocco new file mode 100644 index 0000000000000000000000000000000000000000..840360bf8471609879019862c6b3f3533623c4bc --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/dtrsm.sirocco @@ -0,0 +1,188 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +5 +#################### +# COMB_4 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cpu0_impl0 (Comb4) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +ff82dda0 14745600 0.000000e+00 3.428845e+04 6.014106e+03 4.670087e+07 1.650564e+12 1362 +5831f4e0 102400 0.000000e+00 4.315566e+01 9.048618e+00 2.734774e+05 1.232096e+07 6337 +6a2f38af 3097600 0.000000e+00 3.493952e+03 6.537880e+02 8.623074e+06 3.118353e+10 2468 +0e8bce2b 33177600 0.000000e+00 1.022247e+05 1.393583e+04 9.251336e+07 9.632909e+12 905 +f001bd15 58982400 0.000000e+00 2.235792e+05 2.485110e+04 1.562819e+08 3.537307e+13 699 + +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda2_impl0 (Comb0) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +ff82dda0 14745600 0.000000e+00 3.276119e+03 3.115623e+02 8.157537e+05 2.696677e+09 249 +5831f4e0 102400 0.000000e+00 5.400294e+01 1.227261e+01 9.720530e+02 5.520483e+04 18 +6a2f38af 3097600 0.000000e+00 1.059018e+03 1.208041e+02 2.509872e+05 2.692586e+08 237 +0e8bce2b 33177600 0.000000e+00 7.073186e+03 6.003818e+02 1.082197e+06 7.709734e+09 153 +f001bd15 58982400 0.000000e+00 1.275670e+04 1.000532e+03 2.462043e+06 3.160076e+10 193 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda1_impl0 (Comb1) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +ff82dda0 14745600 0.000000e+00 3.300871e+03 2.581032e+02 6.568733e+05 2.181511e+09 199 +5831f4e0 102400 0.000000e+00 1.639117e+02 3.695355e+01 1.966940e+03 3.387912e+05 12 +6a2f38af 3097600 0.000000e+00 1.035320e+03 1.634986e+02 2.370884e+05 2.515840e+08 229 +0e8bce2b 33177600 0.000000e+00 7.177520e+03 7.682785e+02 1.342196e+06 9.744017e+09 187 +f001bd15 58982400 0.000000e+00 1.284895e+04 1.132613e+03 2.479846e+06 3.211099e+10 193 + +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +3 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda3_impl0 (Comb3) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +ff82dda0 14745600 0.000000e+00 3.224312e+03 2.905618e+02 8.576671e+05 2.787844e+09 266 +5831f4e0 102400 0.000000e+00 1.238758e+02 2.453256e+01 1.238758e+03 1.594706e+05 10 +6a2f38af 3097600 0.000000e+00 1.043152e+03 1.402538e+02 2.597449e+05 2.758515e+08 249 +0e8bce2b 33177600 0.000000e+00 6.893239e+03 4.958485e+02 1.557872e+06 1.079435e+10 226 +f001bd15 58982400 0.000000e+00 1.233960e+04 7.352896e+02 2.924485e+06 3.621511e+10 237 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda0_impl0 (Comb2) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +ff82dda0 14745600 0.000000e+00 3.226919e+03 2.819444e+02 8.357719e+05 2.717557e+09 259 +5831f4e0 102400 0.000000e+00 7.576700e+01 1.461196e+01 1.288039e+03 1.012205e+05 17 +6a2f38af 3097600 0.000000e+00 1.050995e+03 1.429382e+02 2.385759e+05 2.553801e+08 227 +0e8bce2b 33177600 0.000000e+00 7.077068e+03 7.343420e+02 1.288026e+06 9.213596e+09 182 +f001bd15 58982400 0.000000e+00 1.259917e+04 1.081288e+03 2.797016e+06 3.549963e+10 222 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/sgemm.mirage b/simucore/perfmodels/.starpu/sampling/codelets/45/sgemm.mirage new file mode 100644 index 0000000000000000000000000000000000000000..39075d5e1bb6552d69129735162150c024a673cd --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/sgemm.mirage @@ -0,0 +1,152 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +4 +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb3_impl0: cpu +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +f09c52ce 716800 0.000000e+00 1.294618e+03 7.368537e+03 7.230573e+07 3.126057e+12 55851 +d46431bb 1228800 0.000000e+00 3.403637e+03 2.032788e+04 1.361567e+09 1.699370e+14 400033 +94526596 7065600 0.000000e+00 3.940425e+04 1.033596e+03 3.067621e+08 1.209605e+13 7785 +24c84a50 11059200 0.000000e+00 8.599788e+04 1.133409e+03 4.587987e+08 3.946257e+13 5335 +d041c8f5 614400 0.000000e+00 9.227503e+02 1.898800e+03 7.965181e+06 3.847205e+10 8632 + +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb0_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +f09c52ce 716800 0.000000e+00 2.284510e+02 2.701578e+02 2.236535e+05 1.225464e+08 979 +d46431bb 1228800 0.000000e+00 2.435959e+02 2.922073e+03 1.528998e+08 5.396680e+12 627678 +94526596 7065600 0.000000e+00 1.432966e+03 1.728954e+03 1.977493e+06 6.958889e+09 1380 +24c84a50 11059200 0.000000e+00 3.057427e+03 3.294077e+02 1.391466e+08 4.303689e+11 45511 +d041c8f5 614400 0.000000e+00 1.550691e+02 3.976203e+01 3.551084e+04 5.868688e+06 229 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb1_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +f09c52ce 716800 0.000000e+00 2.219381e+02 7.148113e+01 2.345885e+05 5.746492e+07 1057 +d46431bb 1228800 0.000000e+00 2.712307e+02 4.605435e+03 1.564442e+08 1.227625e+13 576794 +94526596 7065600 0.000000e+00 1.375911e+03 5.383438e+01 2.267501e+06 3.124656e+09 1648 +24c84a50 11059200 0.000000e+00 3.028341e+03 1.095661e+02 1.393188e+08 4.224573e+11 46005 +d041c8f5 614400 0.000000e+00 1.568123e+02 3.777848e+01 3.512597e+04 5.827881e+06 224 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb2_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +f09c52ce 716800 0.000000e+00 2.142546e+02 6.233487e+01 2.076127e+05 4.824717e+07 969 +d46431bb 1228800 0.000000e+00 2.619333e+02 1.591424e+03 1.531605e+08 1.521026e+12 584731 +94526596 7065600 0.000000e+00 1.378241e+03 6.538733e+01 2.457404e+06 3.394519e+09 1783 +24c84a50 11059200 0.000000e+00 3.029461e+03 2.553025e+02 1.391886e+08 4.246612e+11 45945 +d041c8f5 614400 0.000000e+00 1.502898e+02 3.546176e+01 3.171115e+04 5.031203e+06 211 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/sgemm.sirocco b/simucore/perfmodels/.starpu/sampling/codelets/45/sgemm.sirocco new file mode 100644 index 0000000000000000000000000000000000000000..f7e01361c25d6519524b044227fdb080135c1f91 --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/sgemm.sirocco @@ -0,0 +1,188 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +5 +#################### +# COMB_4 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cpu0_impl0 (Comb4) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +a7cdf15b 44236800 0.000000e+00 2.633445e+05 5.249424e+04 6.322902e+08 1.731265e+14 2401 +8cfc3ba0 24883200 0.000000e+00 1.120333e+05 2.070542e+04 2.092782e+08 2.424696e+13 1868 +24c84a50 11059200 0.000000e+00 3.623402e+04 6.546678e+03 1.580528e+08 5.913839e+12 4362 +c4a08f5f 2323200 0.000000e+00 3.732336e+03 6.841164e+02 3.950678e+07 1.524065e+11 10585 +e6b94418 76800 0.000000e+00 3.040738e+01 3.904133e+00 2.440131e+06 7.542116e+07 80248 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +3 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda3_impl0 (Comb2) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +a7cdf15b 44236800 0.000000e+00 6.265723e+03 4.806927e+02 8.577149e+07 5.405835e+11 13689 +8cfc3ba0 24883200 0.000000e+00 2.982067e+03 1.577603e+02 2.606923e+07 7.795776e+10 8742 +24c84a50 11059200 0.000000e+00 1.027724e+03 6.416246e+01 1.796770e+07 1.853781e+10 17483 +c4a08f5f 2323200 0.000000e+00 1.681587e+02 2.185477e+01 2.332192e+06 3.988026e+08 13869 +e6b94418 76800 0.000000e+00 4.561876e+01 1.081980e+01 6.934052e+03 3.341172e+05 152 + +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda0_impl0 (Comb0) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +a7cdf15b 44236800 0.000000e+00 6.411657e+03 4.740807e+02 8.565973e+07 5.522235e+11 13360 +8cfc3ba0 24883200 0.000000e+00 2.990259e+03 1.556149e+02 2.622756e+07 7.863960e+10 8771 +24c84a50 11059200 0.000000e+00 1.026941e+03 6.843339e+01 1.818713e+07 1.876005e+10 17710 +c4a08f5f 2323200 0.000000e+00 1.678676e+02 2.188969e+01 2.444656e+06 4.173565e+08 14563 +e6b94418 76800 0.000000e+00 5.712863e+01 1.016253e+01 2.182314e+04 1.286178e+06 382 + +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda1_impl0 (Comb3) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +a7cdf15b 44236800 0.000000e+00 6.216224e+03 4.119793e+02 8.361443e+07 5.220491e+11 13451 +8cfc3ba0 24883200 0.000000e+00 3.034574e+03 1.617988e+02 2.660715e+07 8.097090e+10 8768 +24c84a50 11059200 0.000000e+00 1.042160e+03 6.826839e+01 1.799915e+07 1.883849e+10 17271 +c4a08f5f 2323200 0.000000e+00 1.706067e+02 2.205696e+01 2.522932e+06 4.376237e+08 14788 +e6b94418 76800 0.000000e+00 4.872868e+01 7.797709e+00 3.376898e+04 1.687655e+06 693 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda2_impl0 (Comb1) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +a7cdf15b 44236800 0.000000e+00 6.193669e+03 4.216424e+02 8.780145e+07 5.463333e+11 14176 +8cfc3ba0 24883200 0.000000e+00 3.030444e+03 1.493135e+02 2.715884e+07 8.250317e+10 8962 +24c84a50 11059200 0.000000e+00 1.042297e+03 6.563263e+01 1.817663e+07 1.902057e+10 17439 +c4a08f5f 2323200 0.000000e+00 1.710487e+02 2.221991e+01 2.555297e+06 4.444559e+08 14939 +e6b94418 76800 0.000000e+00 5.246265e+01 9.697468e+00 1.453215e+04 7.884446e+05 277 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/splgsy.mirage b/simucore/perfmodels/.starpu/sampling/codelets/45/splgsy.mirage new file mode 100644 index 0000000000000000000000000000000000000000..3806709aba973ad720b298c0e5f2a5938df8d1b0 --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/splgsy.mirage @@ -0,0 +1,49 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +1 +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb3_impl0: cpu +# number of entries +11 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +681177a1 57600 0.000000e+00 5.838533e+01 5.385033e-01 5.254680e+02 3.068223e+04 9 +e7960a21 153600 0.000000e+00 2.459287e+02 1.335026e+01 2.678163e+05 6.605781e+07 1089 +412400ed 153600 0.000000e+00 2.806436e+02 3.490577e+02 3.056209e+05 2.184557e+08 1089 +cea37d6d 409600 0.000000e+00 6.539599e+02 3.807974e+02 9.026543e+07 7.904510e+10 138029 +982013a8 774400 0.000000e+00 6.655441e+02 1.147597e+01 1.264534e+04 8.418531e+06 19 +be417c6f 1689600 0.000000e+00 2.476178e+03 1.299370e+01 1.780372e+06 4.408638e+09 719 +471f3021 1689600 0.000000e+00 2.879747e+03 1.833475e+02 2.070538e+06 5.986794e+09 719 +617e5fe6 3686400 0.000000e+00 5.696811e+03 7.164692e+02 1.476556e+08 8.544712e+11 25919 +bec19f89 102400 0.000000e+00 1.893129e+02 2.113629e+02 1.171847e+05 4.983796e+07 619 +dd524d7f 102400 0.000000e+00 1.687059e+02 1.677324e+00 1.044290e+05 1.761953e+07 619 +ad30af9b 25600 0.000000e+00 2.908353e+01 3.783301e-01 5.525870e+02 1.607390e+04 19 diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/splgsy.sirocco b/simucore/perfmodels/.starpu/sampling/codelets/45/splgsy.sirocco new file mode 100644 index 0000000000000000000000000000000000000000..a7d3fadfdf669ab9e14981860c3a359a85cbc0cf --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/splgsy.sirocco @@ -0,0 +1,44 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +1 +#################### +# COMB_4 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cpu0_impl0 (Comb4) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +5104f3b7 14745600 0.000000e+00 3.545004e+04 1.130964e+03 1.871762e+07 6.642158e+11 528 +25ebb669 8294400 0.000000e+00 1.998968e+04 3.810275e+02 4.657595e+06 9.313763e+10 233 +617e5fe6 3686400 0.000000e+00 8.939938e+03 2.153220e+02 1.231923e+07 1.101971e+11 1378 +982013a8 774400 0.000000e+00 2.302314e+03 5.466484e+02 1.138264e+07 2.768379e+10 4944 +ad30af9b 25600 0.000000e+00 8.731844e+01 8.227614e+00 1.389149e+06 1.223753e+08 15909 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/spotrf.mirage b/simucore/perfmodels/.starpu/sampling/codelets/45/spotrf.mirage new file mode 100644 index 0000000000000000000000000000000000000000..2f98e8fea6ca54bff5b2eb7075e3711fbede3f78 --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/spotrf.mirage @@ -0,0 +1,145 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +4 +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb3_impl0: cpu +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +681177a1 57600 0.000000e+00 4.555334e+02 1.090643e+02 4.099801e+03 1.974652e+06 9 +cea37d6d 409600 0.000000e+00 1.132958e+03 3.711145e+02 1.898838e+06 2.382134e+09 1676 +982013a8 774400 0.000000e+00 2.357248e+03 4.801633e+00 2.357248e+04 5.556642e+07 10 +617e5fe6 3686400 0.000000e+00 2.085156e+04 6.096702e+02 1.194795e+07 2.493463e+11 573 +ad30af9b 25600 0.000000e+00 1.312747e+02 3.133704e+00 1.312747e+03 1.724287e+05 10 + +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb0_impl0: cuda +# number of entries +4 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +ad30af9b 25600 0.000000e+00 1.585751e+03 4.642049e+01 1.268601e+04 2.013409e+07 8 +cea37d6d 409600 0.000000e+00 3.513309e+03 1.463148e+02 3.513309e+04 1.236475e+08 10 +617e5fe6 3686400 0.000000e+00 7.780375e+03 3.551701e+03 8.169394e+05 7.680626e+09 105 +982013a8 774400 0.000000e+00 2.812901e+03 7.800857e+00 2.250321e+04 6.329979e+07 8 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb1_impl0: cuda +# number of entries +2 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +cea37d6d 409600 0.000000e+00 3.940066e+03 3.201962e+02 3.940066e+04 1.562664e+08 10 +617e5fe6 3686400 0.000000e+00 1.293071e+04 4.788843e+03 3.491292e+05 5.133679e+09 27 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb2_impl0: cuda +# number of entries +2 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +cea37d6d 409600 0.000000e+00 3.783620e+03 9.621290e+01 3.783620e+04 1.432504e+08 10 +617e5fe6 3686400 0.000000e+00 1.752354e+04 5.786330e+03 1.927589e+05 3.746115e+09 11 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/spotrf.sirocco b/simucore/perfmodels/.starpu/sampling/codelets/45/spotrf.sirocco new file mode 100644 index 0000000000000000000000000000000000000000..98ef5d18d1f0662d35587e6f33139cf7b3d81714 --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/spotrf.sirocco @@ -0,0 +1,188 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +5 +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda0_impl0 (Comb0) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +5104f3b7 14745600 0.000000e+00 1.725922e+04 2.264939e+03 1.052812e+06 1.848364e+10 61 +25ebb669 8294400 0.000000e+00 1.618055e+04 2.196987e+03 7.766664e+05 1.279857e+10 48 +982013a8 774400 0.000000e+00 3.928085e+03 4.967651e+02 1.414111e+05 5.643587e+08 36 +ad30af9b 25600 0.000000e+00 2.070017e+03 2.556262e+02 1.283410e+05 2.697195e+08 62 +617e5fe6 3686400 0.000000e+00 9.570246e+03 1.453408e+03 5.263635e+05 5.153611e+09 55 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda1_impl0 (Comb2) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +5104f3b7 14745600 0.000000e+00 1.689494e+04 1.439976e+03 1.081276e+06 1.840081e+10 64 +25ebb669 8294400 0.000000e+00 1.549399e+04 1.742327e+03 8.211813e+05 1.288426e+10 53 +982013a8 774400 0.000000e+00 3.925510e+03 5.372277e+02 1.334673e+05 5.337401e+08 34 +ad30af9b 25600 0.000000e+00 2.102179e+03 3.123586e+02 1.303351e+05 2.800370e+08 62 +617e5fe6 3686400 0.000000e+00 9.539420e+03 1.257811e+03 4.292739e+05 4.166218e+09 45 + +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +3 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda3_impl0 (Comb3) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +5104f3b7 14745600 0.000000e+00 1.679050e+04 1.864821e+03 5.037149e+05 8.561949e+09 30 +25ebb669 8294400 0.000000e+00 1.650986e+04 2.615948e+03 4.457661e+05 7.544300e+09 27 +982013a8 774400 0.000000e+00 4.072426e+03 6.492225e+02 1.384625e+05 5.782087e+08 34 +ad30af9b 25600 0.000000e+00 2.106632e+03 2.976700e+02 1.390377e+05 2.987493e+08 66 +617e5fe6 3686400 0.000000e+00 9.596093e+03 1.252122e+03 2.686906e+05 2.622279e+09 28 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda2_impl0 (Comb1) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +5104f3b7 14745600 0.000000e+00 1.640619e+04 1.490045e+03 6.398413e+05 1.058394e+10 39 +25ebb669 8294400 0.000000e+00 1.538862e+04 2.385658e+03 6.155449e+05 9.700043e+09 40 +982013a8 774400 0.000000e+00 4.069845e+03 5.836273e+02 1.627938e+05 6.761704e+08 40 +ad30af9b 25600 0.000000e+00 2.134159e+03 2.682985e+02 1.323178e+05 2.868503e+08 62 +617e5fe6 3686400 0.000000e+00 9.181625e+03 8.594056e+02 3.580834e+05 3.316592e+09 39 + +#################### +# COMB_4 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cpu0_impl0 (Comb4) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +5104f3b7 14745600 0.000000e+00 4.292375e+04 3.070461e+03 2.704196e+06 1.166682e+11 63 +25ebb669 8294400 0.000000e+00 1.889580e+04 1.888554e+03 1.473872e+06 2.812818e+10 78 +982013a8 774400 0.000000e+00 1.554382e+03 1.710542e+02 5.595775e+04 8.803307e+07 36 +ad30af9b 25600 0.000000e+00 7.450665e+01 4.146608e+00 4.097866e+03 3.062640e+05 55 +617e5fe6 3686400 0.000000e+00 6.920145e+03 2.464678e+02 2.214446e+05 1.534373e+09 32 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/ssyrk.mirage b/simucore/perfmodels/.starpu/sampling/codelets/45/ssyrk.mirage new file mode 100644 index 0000000000000000000000000000000000000000..a7b90a7562dab95105de1d0f537347c7f8210210 --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/ssyrk.mirage @@ -0,0 +1,152 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +4 +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb3_impl0: cpu +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +21d4368e 211200 0.000000e+00 4.384547e+02 2.467124e+03 4.502929e+05 6.448474e+09 1027 +2c1922b7 819200 0.000000e+00 2.187637e+03 1.929489e+04 1.356401e+08 2.337999e+13 62003 +9027d1ef 2464000 0.000000e+00 1.043099e+04 3.133304e+02 6.008252e+06 6.272858e+10 576 +ff82dda0 7372800 0.000000e+00 4.711101e+04 9.991553e+02 3.678899e+08 1.733946e+13 7809 +3bcdebeb 128000 0.000000e+00 1.793047e+02 8.470485e+00 1.050725e+05 1.888204e+07 586 + +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb0_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +21d4368e 211200 0.000000e+00 8.495404e+01 1.117529e+01 2.123851e+03 1.835519e+05 25 +2c1922b7 819200 0.000000e+00 2.088758e+02 5.428469e+01 4.701795e+05 1.048424e+08 2251 +9027d1ef 2464000 0.000000e+00 7.595415e+02 3.139914e+01 3.797708e+04 2.889446e+07 50 +ff82dda0 7372800 0.000000e+00 1.918088e+03 1.840813e+02 2.902067e+06 5.617688e+09 1513 +3bcdebeb 128000 0.000000e+00 8.027020e+01 4.189133e+00 8.027020e+02 6.460854e+04 10 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb1_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +21d4368e 211200 0.000000e+00 9.381324e+01 2.376146e+01 1.594825e+03 1.592140e+05 17 +2c1922b7 819200 0.000000e+00 2.377755e+02 9.692927e+02 3.723565e+05 1.559839e+09 1566 +9027d1ef 2464000 0.000000e+00 7.604821e+02 3.109833e+01 4.106603e+04 3.128221e+07 54 +ff82dda0 7372800 0.000000e+00 1.912329e+03 1.626543e+02 3.122834e+06 6.015089e+09 1633 +3bcdebeb 128000 0.000000e+00 1.243681e+02 1.081974e+02 1.243681e+03 2.717410e+05 10 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb2_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +21d4368e 211200 0.000000e+00 9.977641e+01 4.508035e+01 1.696199e+03 2.037887e+05 17 +2c1922b7 819200 0.000000e+00 2.086732e+02 6.243217e+01 4.874606e+05 1.108252e+08 2336 +9027d1ef 2464000 0.000000e+00 7.679058e+02 4.183926e+01 2.764461e+04 2.129147e+07 36 +ff82dda0 7372800 0.000000e+00 1.923984e+03 1.842678e+02 3.157258e+06 6.130233e+09 1641 +3bcdebeb 128000 0.000000e+00 9.193080e+01 2.132118e+01 9.193080e+02 8.905865e+04 10 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/ssyrk.sirocco b/simucore/perfmodels/.starpu/sampling/codelets/45/ssyrk.sirocco new file mode 100644 index 0000000000000000000000000000000000000000..9892d9aaa183a439d14a884e4b597fc1d27860da --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/ssyrk.sirocco @@ -0,0 +1,188 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +5 +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda0_impl0 (Comb0) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +f001bd15 29491200 0.000000e+00 3.885487e+03 3.138453e+02 1.266669e+06 4.953736e+09 326 +0e8bce2b 16588800 0.000000e+00 1.989457e+03 1.846987e+02 4.018704e+05 8.063950e+08 202 +ff82dda0 7372800 0.000000e+00 6.844636e+02 6.633616e+01 2.457224e+05 1.697678e+08 359 +6a2f38af 1548800 0.000000e+00 1.274568e+02 1.956594e+01 3.097201e+04 4.040621e+06 243 +5831f4e0 51200 0.000000e+00 6.011745e+01 1.013925e+01 1.322584e+03 8.177208e+04 22 + +#################### +# COMB_4 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cpu0_impl0 (Comb4) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +f001bd15 29491200 0.000000e+00 1.358370e+05 2.496094e+04 3.762684e+08 5.283701e+13 2770 +0e8bce2b 16588800 0.000000e+00 5.960685e+04 1.152639e+04 8.929106e+07 5.521380e+12 1498 +ff82dda0 7372800 0.000000e+00 1.879259e+04 3.534541e+03 7.201320e+07 1.401187e+12 3832 +6a2f38af 1548800 0.000000e+00 2.022561e+03 3.698244e+02 8.274299e+06 1.729480e+10 4091 +5831f4e0 51200 0.000000e+00 2.572545e+01 4.086938e+00 1.642570e+05 4.332233e+06 6385 + +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda1_impl0 (Comb3) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +f001bd15 29491200 0.000000e+00 3.928459e+03 3.071670e+02 1.312105e+06 5.186065e+09 334 +0e8bce2b 16588800 0.000000e+00 1.978866e+03 1.664848e+02 5.065897e+05 1.009569e+09 256 +ff82dda0 7372800 0.000000e+00 6.835967e+02 5.317005e+01 1.893563e+05 1.302264e+08 277 +6a2f38af 1548800 0.000000e+00 1.295589e+02 1.835748e+01 3.588782e+04 4.742936e+06 277 +5831f4e0 51200 0.000000e+00 6.087710e+01 1.044897e+01 6.087710e+02 3.815202e+04 10 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +3 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda3_impl0 (Comb2) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +f001bd15 29491200 0.000000e+00 3.795352e+03 3.099710e+02 1.335964e+06 5.104273e+09 352 +0e8bce2b 16588800 0.000000e+00 1.949808e+03 1.585039e+02 4.952512e+05 9.720259e+08 254 +ff82dda0 7372800 0.000000e+00 6.738891e+02 5.051417e+01 2.459695e+05 1.666876e+08 365 +6a2f38af 1548800 0.000000e+00 1.249379e+02 2.159779e+01 3.198410e+04 4.115441e+06 256 +5831f4e0 51200 0.000000e+00 5.816600e+01 9.053481e+00 1.105154e+03 6.583973e+04 19 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda2_impl0 (Comb1) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +f001bd15 29491200 0.000000e+00 3.938373e+03 2.754392e+02 1.606856e+06 6.359353e+09 408 +0e8bce2b 16588800 0.000000e+00 1.981274e+03 1.832435e+02 4.913559e+05 9.818378e+08 248 +ff82dda0 7372800 0.000000e+00 6.796234e+02 6.194853e+01 2.113629e+05 1.448407e+08 311 +6a2f38af 1548800 0.000000e+00 1.301442e+02 2.060864e+01 2.915229e+04 3.889137e+06 224 +5831f4e0 51200 0.000000e+00 6.400964e+01 1.458943e+01 8.961350e+02 6.034120e+04 14 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/strsm.mirage b/simucore/perfmodels/.starpu/sampling/codelets/45/strsm.mirage new file mode 100644 index 0000000000000000000000000000000000000000..db090607453b29ae0122dd009522951b71fc1627 --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/strsm.mirage @@ -0,0 +1,152 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +4 +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb3_impl0: cpu +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +a39e5f37 563200 0.000000e+00 8.923842e+02 7.961174e+01 9.423577e+05 8.476380e+08 1056 +2c1922b7 819200 0.000000e+00 2.321167e+03 8.622579e+02 1.172422e+08 3.096923e+11 50510 +d9e3b267 5376000 0.000000e+00 2.247960e+04 2.089570e+03 1.240874e+07 2.813536e+11 552 +ff82dda0 7372800 0.000000e+00 4.924951e+04 1.580604e+03 1.982785e+08 9.775180e+12 4026 +5c7bc053 512000 0.000000e+00 6.136563e+02 2.276063e+01 3.589889e+05 2.205989e+08 585 + +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb0_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +a39e5f37 563200 0.000000e+00 8.334046e+02 5.701227e+01 8.334046e+03 6.978136e+06 10 +2c1922b7 819200 0.000000e+00 7.348544e+02 5.094262e+02 3.762455e+06 4.093573e+09 5120 +d9e3b267 5376000 0.000000e+00 4.566982e+03 5.776368e+02 2.877199e+05 1.335032e+09 63 +ff82dda0 7372800 0.000000e+00 6.751149e+03 2.062303e+02 1.956483e+07 1.322083e+11 2898 +5c7bc053 512000 0.000000e+00 7.846744e+02 1.681722e+01 8.631418e+03 6.775963e+06 11 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb1_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +a39e5f37 563200 0.000000e+00 8.257133e+02 2.606249e+01 8.257133e+03 6.824817e+06 10 +2c1922b7 819200 0.000000e+00 7.305507e+02 6.039074e+01 5.107280e+06 3.756623e+09 6991 +d9e3b267 5376000 0.000000e+00 4.774713e+03 2.085345e+02 2.482851e+05 1.187751e+09 52 +ff82dda0 7372800 0.000000e+00 6.750674e+03 1.217143e+03 1.907740e+07 1.329719e+11 2826 +5c7bc053 512000 0.000000e+00 7.910209e+02 3.484258e+01 7.910209e+03 6.269281e+06 10 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for Comb2_impl0: cuda +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +a39e5f37 563200 0.000000e+00 8.146353e+02 1.925266e+01 8.146353e+03 6.640013e+06 10 +2c1922b7 819200 0.000000e+00 7.457934e+02 1.035830e+03 4.127966e+06 9.017358e+09 5535 +d9e3b267 5376000 0.000000e+00 4.891576e+03 2.974729e+02 2.396872e+05 1.176785e+09 49 +ff82dda0 7372800 0.000000e+00 6.725995e+03 2.402193e+02 1.914218e+07 1.289144e+11 2846 +5c7bc053 512000 0.000000e+00 7.984381e+02 2.248878e+01 7.984381e+03 6.380091e+06 10 + diff --git a/simucore/perfmodels/.starpu/sampling/codelets/45/strsm.sirocco b/simucore/perfmodels/.starpu/sampling/codelets/45/strsm.sirocco new file mode 100644 index 0000000000000000000000000000000000000000..a04771f26edf1aa8420f260ea91c93284ddf2182 --- /dev/null +++ b/simucore/perfmodels/.starpu/sampling/codelets/45/strsm.sirocco @@ -0,0 +1,188 @@ +################## +# Performance Model Version +45 + +#################### +# COMBs +# number of combinations +5 +#################### +# COMB_4 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +0 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cpu0_impl0 (Comb4) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +f001bd15 29491200 0.000000e+00 1.262354e+05 2.290170e+04 3.312416e+08 4.319067e+13 2624 +0e8bce2b 16588800 0.000000e+00 5.337615e+04 8.326371e+03 7.563401e+07 4.135291e+12 1417 +ff82dda0 7372800 0.000000e+00 1.770446e+04 3.146495e+03 6.559501e+07 1.198005e+12 3705 +6a2f38af 1548800 0.000000e+00 1.942615e+03 3.132030e+02 9.050645e+06 1.803895e+10 4659 +5831f4e0 51200 0.000000e+00 3.124193e+01 7.098676e+00 1.885451e+05 6.194624e+06 6035 + +#################### +# COMB_1 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +2 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda2_impl0 (Comb1) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +f001bd15 29491200 0.000000e+00 1.305248e+04 1.334385e+03 5.207939e+06 6.868697e+10 399 +0e8bce2b 16588800 0.000000e+00 6.227569e+03 8.472811e+02 1.955457e+06 1.240316e+10 314 +ff82dda0 7372800 0.000000e+00 2.363204e+03 3.410126e+02 1.072895e+06 2.588265e+09 454 +6a2f38af 1548800 0.000000e+00 9.588087e+02 1.079624e+02 1.716268e+05 1.666436e+08 179 +5831f4e0 51200 0.000000e+00 1.189339e+02 2.173609e+01 2.497612e+03 3.069724e+05 21 + +#################### +# COMB_3 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +1 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda1_impl0 (Comb3) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +f001bd15 29491200 0.000000e+00 1.285236e+04 1.196289e+03 4.961010e+06 6.431309e+10 386 +0e8bce2b 16588800 0.000000e+00 5.951177e+03 5.675201e+02 1.690134e+06 1.014976e+10 284 +ff82dda0 7372800 0.000000e+00 2.336819e+03 2.871770e+02 9.136963e+05 2.167389e+09 391 +6a2f38af 1548800 0.000000e+00 9.794784e+02 1.067792e+02 1.557371e+05 1.543540e+08 159 +5831f4e0 51200 0.000000e+00 6.696491e+01 1.309227e+01 2.209842e+03 1.536383e+05 33 + +#################### +# COMB_2 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +3 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda3_impl0 (Comb2) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +f001bd15 29491200 0.000000e+00 1.284788e+04 1.232936e+03 6.231224e+06 8.079530e+10 485 +0e8bce2b 16588800 0.000000e+00 5.870740e+03 6.354548e+02 1.943215e+06 1.154177e+10 331 +ff82dda0 7372800 0.000000e+00 2.366672e+03 3.276943e+02 8.401685e+05 2.026524e+09 355 +6a2f38af 1548800 0.000000e+00 9.462385e+02 1.249538e+02 1.750541e+05 1.685314e+08 185 +5831f4e0 51200 0.000000e+00 1.527756e+02 3.246283e+01 2.597185e+03 4.147017e+05 17 + +#################### +# COMB_0 +# number of types devices +1 +#################### +# DEV_0 +# device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4) +1 +#################### +# DEV_0 +# device id +0 +#################### +# DEV_0 +# number of cores +1 +########## +# number of implementations +1 +##### +# Model for cuda0_impl0 (Comb0) +# number of entries +5 +# sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx +0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0 +# a b c +nan nan nan +# not multiple-regression-base +0 +# hash size flops mean (us) dev (us) sum sum2 n +f001bd15 29491200 0.000000e+00 1.272736e+04 1.188134e+03 5.409128e+06 6.944388e+10 425 +0e8bce2b 16588800 0.000000e+00 5.985624e+03 7.297118e+02 1.675975e+06 1.018085e+10 280 +ff82dda0 7372800 0.000000e+00 2.310110e+03 2.968759e+02 1.016448e+06 2.386886e+09 440 +6a2f38af 1548800 0.000000e+00 9.767572e+02 1.265878e+02 1.670255e+05 1.658835e+08 171 +5831f4e0 51200 0.000000e+00 1.183823e+02 2.064199e+01 1.775735e+03 2.166070e+05 15 +