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Commit b0a3e6fc authored by VIGNET Pierre's avatar VIGNET Pierre
Browse files

[lib] Tests: MCLTranslator: Fix typos

parent 7f4db566
......@@ -65,16 +65,12 @@ from cadbiom.models.guard_transitions.analyser.ana_visitors import TableVisitor
from cadbiom.models.clause_constraints.mcl.MCLAnalyser import MCLAnalyser
# simple reporter
class ErrorRep(object):
"""
Simple error reporter
"""
"""Simple error reporter"""
def __init__(self):
self.mess = ""
self.error = False
pass
def display(self, mess):
"""
......@@ -442,7 +438,6 @@ class TestTransitionClauses(unittest.TestCase):
print("place_clocks", cl_ds.place_clocks)
assert cl_ds.place_clocks == {"_lit2": ["n3"], "_lit0": ["n1"]}
# TODO: check this
print("reporter: ", reporter.mess)
assert reporter.mess == ">> type error -> h is not a state (clock)"
......@@ -494,7 +489,6 @@ class TestTransitionClauses(unittest.TestCase):
print("place_clocks", cl_ds.place_clocks)
assert cl_ds.place_clocks == {"_lit2": ["n3"], "_lit0": ["n1"]}
# TODO: check this
print("reporter: ", reporter.mess)
assert reporter.mess == ">> Default signal:(n2 when n1) is not a clock"
......@@ -890,18 +884,8 @@ class TestFull(unittest.TestCase):
print("inputs:", cl_ds.inputs)
expected = {
"n3",
"h2",
"h3",
"h1",
"_lit2",
"_lit3",
"n1",
"_lit1",
"_lit0",
"n4",
"n2",
"_lit4",
"n3", "h2", "h3", "h1", "_lit2", "_lit3", "n1", "_lit1", "_lit0",
"n4", "n2", "_lit4",
}
assert cl_ds.base_var_set == expected
assert cl_ds.free_clocks == ["h3", "h1", "h2"]
......@@ -983,21 +967,8 @@ class TestFull(unittest.TestCase):
print("inputs:", cl_ds.inputs)
expected = {
"n3",
"h2",
"h3",
"h1",
"_lit6",
"_lit7",
"_lit2",
"_lit3",
"n1",
"_lit1",
"_lit0",
"n4",
"n2",
"_lit5",
"_lit4",
"n3", "h2", "h3", "h1", "_lit6", "_lit7", "_lit2", "_lit3", "n1",
"_lit1", "_lit0", "n4", "n2", "_lit5", "_lit4",
}
assert cl_ds.base_var_set == expected
assert cl_ds.free_clocks == ["h3", "h1", "h2"]
......
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