Skip to content
GitLab
Menu
Projects
Groups
Snippets
Loading...
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
Menu
Open sidebar
VIGNET Pierre
cadbiom
Commits
9a0a4393
Commit
9a0a4393
authored
Feb 14, 2017
by
VIGNET Pierre
Browse files
extract_act_inputs_clocks: Huge improvement: better algo
parent
3b5d0c63
Changes
1
Show whitespace changes
Inline
Side-by-side
cadbiom/models/clause_constraints/mcl/MCLSolutions.py
View file @
9a0a4393
...
@@ -228,14 +228,14 @@ class RawSolution(object):
...
@@ -228,14 +228,14 @@ class RawSolution(object):
"""
"""
extract active __inputs and clocks from a state vector
extract active __inputs and clocks from a state vector
"""
"""
out
=
[]
for
s_varcode
in
s_vector
:
inputs
=
frozenset
(
self
.
__unfolder
.
get_inputs
())
cond1
=
s_varcode
in
self
.
__unfolder
.
get_
input
s
()
free_clocks
=
frozenset
(
self
.
__unfolder
.
get_
free_clock
s
()
)
cond2
=
s_varcode
in
self
.
__unfolder
.
get_free_clocks
()
if
cond1
or
cond2
:
return
[
s_varcode
for
s_varcode
in
s_vector
if
s_varcode
>
0
:
if
(
s_varcode
>
0
)
out
.
append
(
s_varcode
)
and
((
s_varcode
in
inputs
)
return
out
or
(
s_varcode
in
free_clocks
))]
def
extract_act_input_clock_seq
(
self
):
def
extract_act_input_clock_seq
(
self
):
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment