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Commit 10e9c560 authored by VIGNET Pierre's avatar VIGNET Pierre
Browse files

[lib] Tests: MCLTranslator: Tests are now real tests that do something...

parent f3310efc
......@@ -45,14 +45,21 @@ Unitary tests for the translators
from __future__ import print_function
import pkg_resources
import unittest
import sys
from cadbiom.models.clause_constraints.CLDynSys import CLDynSys
from cadbiom.models.clause_constraints.mcl.MCLTranslators import MCLSigExprVisitor, \
gen_transition_clock, gen_transition_list_clock, \
gen_simple_evolution, GT2Clauses
from cadbiom.models.biosignal.sig_expr import SigIdentExpr, \
SigSyncBinExpr, SigWhenExpr, SigDefaultExpr
from cadbiom.models.clause_constraints.mcl.MCLTranslators import (
MCLSigExprVisitor,
gen_transition_clock,
gen_transition_list_clock,
gen_simple_evolution,
GT2Clauses,
)
from cadbiom.models.biosignal.sig_expr import (
SigIdentExpr,
SigSyncBinExpr,
SigWhenExpr,
SigDefaultExpr,
)
from cadbiom.models.guard_transitions.chart_model import ChartModel
from cadbiom.models.guard_transitions.analyser.ana_visitors import TableVisitor
from cadbiom.models.clause_constraints.mcl.MCLAnalyser import MCLAnalyser
......@@ -63,6 +70,7 @@ class ErrorRep(object):
"""
Simple error reporter
"""
def __init__(self):
self.mess = ""
self.error = False
......@@ -73,263 +81,317 @@ class ErrorRep(object):
set error and print
"""
self.error = True
self.mess += '\n>> '+mess
print('\n DISPLAY CALL>> '+mess)
self.mess += ">> " + mess
print(" DISPLAY CALL>> " + mess)
TRACE_FILE = sys.stdout
#TRACE_FILE = open("/tmp/testMCLTranslator.txt",'w')
class TestTransitionClauses(unittest.TestCase):
"""
Test of transitions into clauses
"""
def test_no_cond(self): #OK
def test_no_cond(self): # OK
"""
n1 --> n2; []
"""
model = ChartModel("Test")
root = model.get_root()
nn1 = root.add_simple_node('n1', 0, 0)
nn2 = root.add_simple_node('n2', 0, 0)
nn1 = root.add_simple_node("n1", 0, 0)
nn2 = root.add_simple_node("n2", 0, 0)
trans = root.add_transition(nn1, nn2)
tvisit = TableVisitor(None) # no error display
tvisit = TableVisitor(None) # no error display
model.accept(tvisit)
reporter = ErrorRep()
cl_ds = CLDynSys(tvisit, reporter)
TRACE_FILE.write('\ntestNoCond')
TRACE_FILE.write( '\n\nn1 --> n2; []\n')
htr = gen_transition_clock(trans, cl_ds, None, reporter)
TRACE_FILE.write( 'Transition clock:'+ htr.__str__()+'\n')
for cla in cl_ds.clauses:
TRACE_FILE.write( cla.__str__()+'\n')
mess = 'free clocks registered:' + cl_ds.free_clocks.__str__() + '\n'
TRACE_FILE.write(mess)
TRACE_FILE.write( 'reporter: '+ reporter.mess+'\n')
def test_cond(self): #OK
event_literal = gen_transition_clock(trans, cl_ds, None, reporter)
print("Transition clock:", str(event_literal))
assert str(event_literal) == "n1"
assert cl_ds.clauses == []
print("free clocks registered:", cl_ds.free_clocks)
assert cl_ds.free_clocks == []
print("reporter:", reporter.mess)
assert reporter.mess == ""
def test_cond(self): # OK
"""
n1 --> n2; [not n3]
"""
model = ChartModel("Test")
root = model.get_root()
nn1 = root.add_simple_node('n1', 0, 0)
nn2 = root.add_simple_node('n2', 0, 0)
nn3 = root.add_simple_node('n3', 0, 0)
nn1 = root.add_simple_node("n1", 0, 0)
nn2 = root.add_simple_node("n2", 0, 0)
root.add_simple_node("n3", 0, 0)
trans = root.add_transition(nn1, nn2)
trans.set_condition("not n3")
tvisit = TableVisitor(None) # no error display
tvisit = TableVisitor(None) # no error display
model.accept(tvisit)
reporter = ErrorRep()
cl_ds = CLDynSys( tvisit.tab_symb, None)
TRACE_FILE.write('\ntestCond')
TRACE_FILE.write( '\n\nn1 --> n2; [not n3]'+'\n')
htr = gen_transition_clock(trans, cl_ds, None, reporter)
TRACE_FILE.write( 'Transition clock:' + htr.__str__()+'\n')
for cla in cl_ds.clauses:
TRACE_FILE.write( cla.__str__() + '\n')
mess = 'free clocks registered:' + cl_ds.free_clocks.__str__()+'\n'
TRACE_FILE.write(mess)
TRACE_FILE.write( 'reporter: '+ reporter.mess+'\n')
def test_no_cond_event(self): #OK
cl_ds = CLDynSys(tvisit.tab_symb, None)
event_literal = gen_transition_clock(trans, cl_ds, None, reporter)
print("Transition clock:", str(event_literal))
assert str(event_literal) == "_lit0"
expected = ["$n1, not _lit0$", "$not n3, not _lit0$", "$not n1, n3, _lit0$"]
assert [str(clause) for clause in cl_ds.clauses] == expected
print("free clocks registered:", cl_ds.free_clocks)
assert cl_ds.free_clocks == []
print("reporter:", reporter.mess)
assert reporter.mess == ""
def test_no_cond_event(self): # OK
"""
n1 --> n2; h[]
"""
model = ChartModel("Test")
root = model.get_root()
nn1 = root.add_simple_node('n1', 0, 0)
nn2 = root.add_simple_node('n2', 0, 0)
nn1 = root.add_simple_node("n1", 0, 0)
nn2 = root.add_simple_node("n2", 0, 0)
trans = root.add_transition(nn1, nn2)
trans.set_event('h')
trans.set_event("h")
tvisit = TableVisitor(None) # no error display
tvisit = TableVisitor(None) # no error display
model.accept(tvisit)
reporter = ErrorRep()
cl_ds = CLDynSys(tvisit.tab_symb, reporter)
TRACE_FILE.write('\ntestNoCondEvent')
TRACE_FILE.write( '\n\nn1 --> n2; h[]'+'\n')
htr = gen_transition_clock(trans, cl_ds, None, reporter)
TRACE_FILE.write( 'Transition clock:'+ htr.__str__()+'\n')
for cla in cl_ds.clauses:
TRACE_FILE.write( cla.__str__() + '\n')
mess = 'free clocks registered:' +cl_ds.free_clocks.__str__()+'\n'
TRACE_FILE.write(mess)
TRACE_FILE.write( 'reporter: '+ reporter.mess+'\n')
TRACE_FILE.write( '---------- opti ----------------\n')
event_literal = gen_transition_clock(trans, cl_ds, None, reporter)
print("Transition clock:", str(event_literal))
assert str(event_literal) == "_lit0"
expected = ["$not _lit0, h$", "$not _lit0, n1$", "$not h, not n1, _lit0$"]
assert [str(clause) for clause in cl_ds.clauses] == expected
print("free clocks registered:", cl_ds.free_clocks)
assert cl_ds.free_clocks == ["h"]
print("reporter: ", reporter.mess)
assert reporter.mess == ""
print("---------- opti ----------------")
sed = dict()
tvisit = TableVisitor(None) # no error display
tvisit = TableVisitor(None) # no error display
model.accept(tvisit)
cl_ds = CLDynSys(tvisit.tab_symb, reporter)
htr = gen_transition_clock(trans, cl_ds, sed, reporter)
TRACE_FILE.write( 'Transition clock:'+ htr.__str__()+'\n')
for cla in cl_ds.clauses:
TRACE_FILE.write( cla.__str__()+'\n')
mess = 'free clocks registered:' + cl_ds.free_clocks.__str__() + '\n'
TRACE_FILE.write(mess)
TRACE_FILE.write( 'reporter: '+ reporter.mess+'\n')
event_literal = gen_transition_clock(trans, cl_ds, sed, reporter)
print("Transition clock:", str(event_literal))
assert str(event_literal) == "_lit0"
assert [str(clause) for clause in cl_ds.clauses] == expected
print("free clocks registered:", cl_ds.free_clocks)
assert cl_ds.free_clocks == ["h"]
print("reporter: ", reporter.mess)
assert reporter.mess == ""
def test_cond_event(self): #OK
def test_cond_event(self): # OK
"""
n1 --> n2; h[not n3]
"""
model = ChartModel("Test")
root = model.get_root()
nn1 = root.add_simple_node('n1', 0, 0)
nn2 = root.add_simple_node('n2', 0, 0)
nn3 = root.add_simple_node('n3', 0, 0)
nn1 = root.add_simple_node("n1", 0, 0)
nn2 = root.add_simple_node("n2", 0, 0)
root.add_simple_node("n3", 0, 0)
trans = root.add_transition(nn1, nn2)
trans.set_condition("not n3")
trans.set_event('h')
trans.set_event("h")
tvisit = TableVisitor(None) # no error display
tvisit = TableVisitor(None) # no error display
model.accept(tvisit)
reporter = ErrorRep()
cl_ds = CLDynSys( tvisit.tab_symb, None)
TRACE_FILE.write('\ntestCondEvent')
TRACE_FILE.write( '\n\nn1 --> n2; h[not n3]'+'\n')
htr = gen_transition_clock(trans, cl_ds, None, reporter)
TRACE_FILE.write( 'Transition clock:'+ htr.__str__()+'\n')
for cla in cl_ds.clauses:
TRACE_FILE.write( cla.__str__()+'\n')
mess = 'free clocks registered:'+ cl_ds.free_clocks.__str__()+'\n'
TRACE_FILE.write(mess)
TRACE_FILE.write( 'reporter: '+ reporter.mess+'\n')
TRACE_FILE.write( '---------- opti ----------------\n')
cl_ds = CLDynSys(tvisit.tab_symb, None)
event_literal = gen_transition_clock(trans, cl_ds, None, reporter)
print("Transition clock:", str(event_literal))
assert str(event_literal) == "_lit1"
expected = [
"$n1, not _lit0$",
"$not n3, not _lit0$",
"$not n1, n3, _lit0$",
"$not _lit1, h$",
"$not _lit1, _lit0$",
"$not h, not _lit0, _lit1$",
]
assert [str(clause) for clause in cl_ds.clauses] == expected
print("free clocks registered:", cl_ds.free_clocks)
assert cl_ds.free_clocks == ["h"]
print("reporter: ", reporter.mess)
assert reporter.mess == ""
print("---------- opti ----------------")
sed = dict()
tvisit = TableVisitor(None) # no error display
tvisit = TableVisitor(None) # no error display
model.accept(tvisit)
reporter = ErrorRep()
cl_ds = CLDynSys( tvisit.tab_symb, None)
TRACE_FILE.write('\ntestCondEvent')
TRACE_FILE.write( '\n\nn1 --> n2; h[not n3]'+'\n')
htr = gen_transition_clock(trans, cl_ds, sed, reporter)
TRACE_FILE.write( 'Transition clock:'+ htr.__str__()+'\n')
for cla in cl_ds.clauses:
TRACE_FILE.write( cla.__str__()+'\n')
mess = 'free clocks registered:'+ cl_ds.free_clocks.__str__()+'\n'
TRACE_FILE.write(mess)
TRACE_FILE.write( 'reporter: '+ reporter.mess+'\n')
cl_ds = CLDynSys(tvisit.tab_symb, None)
event_literal = gen_transition_clock(trans, cl_ds, sed, reporter)
print("Transition clock:", str(event_literal))
assert str(event_literal) == "_lit1"
assert [str(clause) for clause in cl_ds.clauses] == expected
print("free clocks registered:", cl_ds.free_clocks)
assert cl_ds.free_clocks == ["h"]
print("reporter: ", reporter.mess)
assert reporter.mess == ""
def test_perm_no_cond_event(self): #OK
def test_perm_no_cond_event(self): # OK
"""
n1/p --> n2; h[];
"""
model = ChartModel("Test")
root = model.get_root()
nn1 = root.add_perm_node('n1', 0, 0)
nn2 = root.add_simple_node('n2', 0, 0)
nn1 = root.add_perm_node("n1", 0, 0)
nn2 = root.add_simple_node("n2", 0, 0)
trans = root.add_transition(nn1, nn2)
trans.set_event('h')
trans.set_event("h")
tvisit = TableVisitor(None) # no error display
tvisit = TableVisitor(None) # no error display
model.accept(tvisit)
reporter = ErrorRep()
cl_ds = CLDynSys( tvisit.tab_symb, None)
TRACE_FILE.write('\ntestPermNoCondEvent')
TRACE_FILE.write( '\n\nn1/p --> n2; h[]'+'\n' )
htr = gen_transition_clock(trans, cl_ds, None, reporter)
TRACE_FILE.write( 'Transition clock:'+htr.__str__()+'\n')
for cla in cl_ds.clauses:
TRACE_FILE.write( cla.__str__()+'\n')
mess = 'free clocks registered:'+ cl_ds.free_clocks.__str__()+'\n'
TRACE_FILE.write(mess)
TRACE_FILE.write( 'reporter: '+ reporter.mess+'\n')
def test_perm_cond_event(self): #OK
cl_ds = CLDynSys(tvisit.tab_symb, None)
event_literal = gen_transition_clock(trans, cl_ds, None, reporter)
print("Transition clock:", str(event_literal))
assert str(event_literal) == "_lit0"
expected = ["$not _lit0, h$", "$not _lit0, n1$", "$not h, not n1, _lit0$"]
assert [str(clause) for clause in cl_ds.clauses] == expected
print("free clocks registered:", cl_ds.free_clocks)
assert cl_ds.free_clocks == ["h"]
print("reporter: ", reporter.mess)
assert reporter.mess == ""
def test_perm_cond_event(self): # OK
"""
n4;
n1/p --> n2; h[n4];
"""
model = ChartModel("Test")
root = model.get_root()
nn1 = root.add_perm_node('n1', 0, 0)
nn2 = root.add_simple_node('n2', 0, 0)
nn4 = root.add_simple_node('n4', 0, 0)
nn1 = root.add_perm_node("n1", 0, 0)
nn2 = root.add_simple_node("n2", 0, 0)
root.add_simple_node("n4", 0, 0)
trans = root.add_transition(nn1, nn2)
trans.set_condition("n4")
trans.set_event('h')
trans.set_event("h")
tvisit = TableVisitor(None) # no error display
tvisit = TableVisitor(None) # no error display
model.accept(tvisit)
reporter = ErrorRep()
cl_ds = CLDynSys( tvisit.tab_symb, None)
TRACE_FILE.write('\ntestPermCondEvent')
TRACE_FILE.write( '\n\nn1/p --> n2; h[n4]' +'\n')
htr = gen_transition_clock(trans, cl_ds, None, reporter)
TRACE_FILE.write( 'Transition clock:'+ htr.__str__()+'\n')
for cla in cl_ds.clauses:
TRACE_FILE.write(cla.__str__()+'\n')
mess = 'free clocks registered:'+ cl_ds.free_clocks.__str__()+'\n'
TRACE_FILE.write(mess)
TRACE_FILE.write( 'reporter: '+ reporter.mess+'\n')
def test_input_cond_event(self): #OK
cl_ds = CLDynSys(tvisit.tab_symb, None)
event_literal = gen_transition_clock(trans, cl_ds, None, reporter)
print("Transition clock:", str(event_literal))
assert str(event_literal) == "_lit0"
expected = ["$not _lit0, h$", "$not _lit0, n4$", "$not h, not n4, _lit0$"]
assert [str(clause) for clause in cl_ds.clauses] == expected
print("free clocks registered:", cl_ds.free_clocks)
assert cl_ds.free_clocks == ["h"]
print("reporter: ", reporter.mess)
assert reporter.mess == ""
def test_input_cond_event(self): # OK
"""
n4/i;
n1/i --> n2; h[n4];
"""
model = ChartModel("Test")
root = model.get_root()
nn1 = root.add_input_node('n1', 0, 0)
nn2 = root.add_simple_node('n2', 0, 0)
nn4 = root.add_input_node('n4', 0, 0)
nn1 = root.add_input_node("n1", 0, 0)
nn2 = root.add_simple_node("n2", 0, 0)
root.add_input_node("n4", 0, 0)
trans = root.add_transition(nn1, nn2)
trans.set_condition("n4")
trans.set_event('h')
trans.set_event("h")
tvisit = TableVisitor(None) # no error display
tvisit = TableVisitor(None) # no error display
model.accept(tvisit)
reporter = ErrorRep()
cl_ds = CLDynSys( tvisit.tab_symb, None)
TRACE_FILE.write('\ntestInputCondEvent')
TRACE_FILE.write( '\n\nn1/i --> n2; h[n4]'+'\n')
htr = gen_transition_clock(trans, cl_ds, None, reporter)
TRACE_FILE.write( 'Transition clock:' +htr.__str__()+'\n')
for cla in cl_ds.clauses:
TRACE_FILE.write( cla.__str__()+'\n')
mess = 'free clocks registered:'+ cl_ds.free_clocks.__str__()+'\n'
TRACE_FILE.write(mess)
TRACE_FILE.write( 'reporter: '+ reporter.mess+'\n')
cl_ds = CLDynSys(tvisit.tab_symb, None)
event_literal = gen_transition_clock(trans, cl_ds, None, reporter)
print("Transition clock:", str(event_literal))
assert str(event_literal) == "_lit1"
expected = [
"$n1, not _lit0$",
"$n4, not _lit0$",
"$not n1, not n4, _lit0$",
"$not _lit1, h$",
"$not _lit1, _lit0$",
"$not h, not _lit0, _lit1$",
]
assert [str(clause) for clause in cl_ds.clauses] == expected
print("free clocks registered:", cl_ds.free_clocks)
assert cl_ds.free_clocks == ["h"]
print("reporter: ", reporter.mess)
assert reporter.mess == ""
# complex events
def test_no_cond_event_when1(self): #OK
def test_no_cond_event_when1(self): # OK
"""
n1 --> n2; h when n3[]
n3;
"""
model = ChartModel("Test")
root = model.get_root()
nn1 = root.add_simple_node('n1', 0, 0)
nn2 = root.add_simple_node('n2', 0, 0)
nn3 = root.add_simple_node('n3', 0, 0)
nn1 = root.add_simple_node("n1", 0, 0)
nn2 = root.add_simple_node("n2", 0, 0)
root.add_simple_node("n3", 0, 0)
trans = root.add_transition(nn1, nn2)
trans.set_event('h when n3')
trans.set_event("h when n3")
tvisit = TableVisitor(None) # no error display
tvisit = TableVisitor(None) # no error display
model.accept(tvisit)
reporter = ErrorRep()
cl_ds = CLDynSys(tvisit.tab_symb, reporter)
TRACE_FILE.write('\ntestNoCondEventWhen1')
TRACE_FILE.write( '\n\nn1 --> n2; h when n3[]; n3;'+'\n')
htr = gen_transition_clock(trans, cl_ds, None, reporter)
TRACE_FILE.write( 'Transition clock:'+ htr.__str__()+'\n')
for cla in cl_ds.clauses:
TRACE_FILE.write( cla.__str__()+'\n')
mess = 'free clocks registered:' +cl_ds.free_clocks.__str__()+'\n'
TRACE_FILE.write(mess)
TRACE_FILE.write( 'place_clocks'+ cl_ds.place_clocks.__str__()+'\n')
TRACE_FILE.write( 'reporter: '+ reporter.mess+'\n')
def test_no_cond_event_when2(self): #OK
event_literal = gen_transition_clock(trans, cl_ds, None, reporter)
print("Transition clock:", str(event_literal))
assert str(event_literal) == "_lit1"
expected = [
"$not h, not n3, _lit0$",
"$not _lit0, h$",
"$not _lit0, n3$",
"$not _lit1, _lit0$",
"$not _lit1, n1$",
"$not _lit0, not n1, _lit1$",
]
assert [str(clause) for clause in cl_ds.clauses] == expected
print("free clocks registered:", cl_ds.free_clocks)
assert cl_ds.free_clocks == ["h"]
print("place_clocks", cl_ds.place_clocks)
assert cl_ds.place_clocks == {"_lit0": ["n1"]}
print("reporter: ", reporter.mess)
assert reporter.mess == ""
def test_no_cond_event_when2(self): # OK
"""
n1 --> n2; h when n3[]
n3 --> n1 ; h2 when h[]
......@@ -337,34 +399,54 @@ class TestTransitionClauses(unittest.TestCase):
"""
model = ChartModel("Test")
root = model.get_root()
nn1 = root.add_simple_node('n1', 0, 0)
nn2 = root.add_simple_node('n2', 0, 0)
nn3 = root.add_simple_node('n3', 0, 0)
nn1 = root.add_simple_node("n1", 0, 0)
nn2 = root.add_simple_node("n2", 0, 0)
nn3 = root.add_simple_node("n3", 0, 0)
tr1 = root.add_transition(nn1, nn2)
tr1.set_event('h when n3')
tr1.set_event("h when n3")
tr2 = root.add_transition(nn3, nn1)
tr2.set_event('h2 when h')
tr2.set_event("h2 when h")
reporter = ErrorRep()
tvisit = TableVisitor(reporter) # no error display
tvisit = TableVisitor(reporter) # no error display
model.accept(tvisit)
cl_ds = CLDynSys(tvisit.tab_symb, reporter)
TRACE_FILE.write('\ntestNoCondEventWhen1')
mess = '\n\nn1 --> n2; h when n3[]; n3 --> n1 ; h2 when h[];'+'\n'
TRACE_FILE.write(mess)
htr = gen_transition_clock(tr1, cl_ds, None, reporter)
TRACE_FILE.write( 'Transition clock:'+ htr.__str__()+'\n')
htr = gen_transition_clock(tr2, cl_ds, None, reporter)
TRACE_FILE.write( 'Transition clock:'+ htr.__str__()+'\n')
for cla in cl_ds.clauses:
TRACE_FILE.write( cla.__str__()+'\n')
mess = 'free clocks registered:' +cl_ds.free_clocks.__str__()+'\n'
TRACE_FILE.write(mess)
TRACE_FILE.write( 'place_clocks'+ cl_ds.place_clocks.__str__()+'\n')
TRACE_FILE.write( 'reporter: '+ reporter.mess+'\n')
def test_no_cond_event_when3(self): #OK
event_literal = gen_transition_clock(tr1, cl_ds, None, reporter)
print("Transition clock:", str(event_literal))
assert str(event_literal) == "_lit1"
event_literal = gen_transition_clock(tr2, cl_ds, None, reporter)
print("Transition clock:", str(event_literal))
assert str(event_literal) == "_lit3"
expected = [
"$not h, not n3, _lit0$",
"$not _lit0, h$",
"$not _lit0, n3$",
"$not _lit1, _lit0$",
"$not _lit1, n1$",
"$not _lit0, not n1, _lit1$",
"$not h2, not h, _lit2$",
"$not _lit2, h2$",
"$not _lit2, h$",
"$not _lit3, _lit2$",