Commit 69ebfed3 authored by DEANTONI Julien's avatar DEANTONI Julien

minor modifications in the examples

parent 4629848e
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -16,9 +16,9 @@ ClockConstraintSystem MySpec {
Relation r1[Alternates](AlternatesLeftClock -> c1, AlternatesRightClock -> c2 )
Clock c1 //-> evt1("TheModel::TheClass::p1"):start
Clock c2 //-> evt2("TheModel::TheClass::p1"): finish
Relation r2[Alternates](AlternatesLeftClock ->A, AlternatesRightClock -> B )
Clock A
Clock B
// Relation r2[Alternates](AlternatesLeftClock ->A, AlternatesRightClock -> B )
// Clock A
// Clock B
}
......
......@@ -3,44 +3,11 @@ digraph {
start=0;
node [style="filled"]
0 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="11826886"];
1 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="705891314"];
2 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="163549361"];
3 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="1278064645"];
4 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="202472521"];
5 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="1888578235"];
6 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="1900645342"];
7 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="1280019398"];
8 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="1378842774"];
0 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="1166699485"];
1 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="504416653"];
2 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="1126212805"];
0 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[A]"];
0 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[A]"];
0 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[c1, A]"];
0 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[c1, A]"];
0 -> 3 [penwidth="1", color="#aaaaaa", style="solid", label="[c1]"];
0 -> 3 [penwidth="1", color="#aaaaaa", style="solid", label="[c1]"];
1 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[c1]"];
1 -> 4 [penwidth="1", color="#aaaaaa", style="solid", label="[B, c1]"];
1 -> 5 [penwidth="1", color="#aaaaaa", style="solid", label="[B]"];
2 -> 4 [penwidth="1", color="#aaaaaa", style="solid", label="[B]"];
2 -> 6 [penwidth="1", color="#aaaaaa", style="solid", label="[c2, B]"];
2 -> 7 [penwidth="1", color="#aaaaaa", style="solid", label="[c2]"];
3 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[A]"];
3 -> 7 [penwidth="1", color="#aaaaaa", style="solid", label="[c2, A]"];
3 -> 8 [penwidth="1", color="#aaaaaa", style="solid", label="[c2]"];
4 -> 7 [penwidth="1", color="#aaaaaa", style="solid", label="[c2, A]"];
4 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[A]"];
4 -> 6 [penwidth="1", color="#aaaaaa", style="solid", label="[c2]"];
5 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[c1, A]"];
5 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[A]"];
5 -> 4 [penwidth="1", color="#aaaaaa", style="solid", label="[c1]"];
6 -> 7 [penwidth="1", color="#aaaaaa", style="solid", label="[A]"];
6 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[c1, A]"];
6 -> 4 [penwidth="1", color="#aaaaaa", style="solid", label="[c1]"];
7 -> 4 [penwidth="1", color="#aaaaaa", style="solid", label="[B, c1]"];
7 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[c1]"];
7 -> 6 [penwidth="1", color="#aaaaaa", style="solid", label="[B]"];
8 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[c1, A]"];
8 -> 3 [penwidth="1", color="#aaaaaa", style="solid", label="[c1]"];
8 -> 7 [penwidth="1", color="#aaaaaa", style="solid", label="[A]"];
0 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[c1]"];
1 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[c2]"];
2 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[c1]"];
}
\ No newline at end of file
Specification MySpec {
Clock c1 c2 A B
[
Precedence c1 <= (max:1) c2
Precedence A <= (max:1) B
]
}
......@@ -11,8 +11,8 @@ ClockConstraintSystem MySpec {
}
entryBlock main
Block main {
Clock F
Clock G
// Clock F
// Clock G
Clock c1
Clock c2
......
/*
* CCSL specification
* @author: jdeanton
* date : Thu August 30 2018 03:39:44 CEST
*/
ClockConstraintSystem causalityLoop1 {
imports {
// import statements
import "platform:/plugin/fr.inria.aoste.timesquare.ccslkernel.model/ccsllibrary/kernel.ccslLib" as lib0;
import "platform:/plugin/fr.inria.aoste.timesquare.ccslkernel.model/ccsllibrary/CCSL.ccslLib" as lib1;
}
entryBlock main
Block main {
Clock a
Clock b
Clock c
Clock d
Clock C1
Clock C2
Relation relation_4[Alternates]( AlternatesLeftClock-> C1 , AlternatesRightClock-> C2 )
Relation relation_5[SubClock]( LeftClock -> a , RightClock -> C1 )
Relation relation_0[Precedes]( LeftClock -> a , RightClock -> b )
Relation relation_1[Precedes]( LeftClock -> b , RightClock -> c )
Relation relation_2[Precedes]( LeftClock -> c , RightClock -> d )
Relation relation_3[Precedes]( LeftClock -> d , RightClock -> a )
}
}
......@@ -15,12 +15,19 @@ ClockConstraintSystem MySpec {
entryBlock main
Block main {
Clock a
Clock sup
Clock b
Clock c
Relation bSubOfc[SubClock]( LeftClock-> b , RightClock-> c )
Clock d
Relation bPrecd[Precedes]( LeftClock-> b ,RightClock-> d )
Relation cAlterd[Alternates]( AlternatesLeftClock-> c , AlternatesRightClock-> d )
Relation bdef[Coincides]( Clock2 -> b , Clock1 -> bexp)
Expression bexp=PeriodicOffsetP( PeriodicOffsetPBaseClock -> sup ,PeriodicOffsetPPeriod -> three )
Relation a_SubOf_sup[SubClock]( LeftClock-> a , RightClock-> sup )
Relation a_Prec_b[Precedes]( LeftClock-> a ,RightClock-> b )
Clock newClock
Relation relation_0[Precedes]( LeftClock -> newClock , RightClock -> b )
}
}
digraph {
rankdir=LR;
start=0;
node [style="filled"]
0 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="127696479"];
1 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="956412655"];
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6 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="691872672"];
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10 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="1612405362"];
11 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="575553227"];
0 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[e1, b, c]"];
0 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[e1, c]"];
0 -> 3 [penwidth="1", color="#aaaaaa", style="solid", label="[e1]"];
0 -> 4 [penwidth="1", color="#aaaaaa", style="solid", label="[b, c]"];
0 -> 5 [penwidth="1", color="#aaaaaa", style="solid", label="[c]"];
1 -> 6 [penwidth="1", color="#aaaaaa", style="solid", label="[e2, d]"];
1 -> 7 [penwidth="1", color="#aaaaaa", style="solid", label="[e2]"];
1 -> 8 [penwidth="1", color="#aaaaaa", style="solid", label="[d]"];
2 -> 9 [penwidth="1", color="#aaaaaa", style="solid", label="[e2]"];
3 -> 7 [penwidth="1", color="#aaaaaa", style="solid", label="[e2, b, c]"];
3 -> 9 [penwidth="1", color="#aaaaaa", style="solid", label="[e2, c]"];
3 -> 10 [penwidth="1", color="#aaaaaa", style="solid", label="[e2]"];
3 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[b, c]"];
3 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[c]"];
4 -> 8 [penwidth="1", color="#aaaaaa", style="solid", label="[d, e1]"];
4 -> 11 [penwidth="1", color="#aaaaaa", style="solid", label="[d]"];
4 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[e1]"];
5 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[e1]"];
6 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[e1, b, c]"];
6 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[e1, c]"];
6 -> 8 [penwidth="1", color="#aaaaaa", style="solid", label="[e1]"];
6 -> 7 [penwidth="1", color="#aaaaaa", style="solid", label="[b, c]"];
6 -> 9 [penwidth="1", color="#aaaaaa", style="solid", label="[c]"];
7 -> 8 [penwidth="1", color="#aaaaaa", style="solid", label="[d, e1]"];
7 -> 6 [penwidth="1", color="#aaaaaa", style="solid", label="[d]"];
7 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[e1]"];
8 -> 7 [penwidth="1", color="#aaaaaa", style="solid", label="[e2, b, c]"];
8 -> 9 [penwidth="1", color="#aaaaaa", style="solid", label="[e2, c]"];
8 -> 6 [penwidth="1", color="#aaaaaa", style="solid", label="[e2]"];
8 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[b, c]"];
8 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[c]"];
9 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[e1]"];
10 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[e1, b, c]"];
10 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[e1, c]"];
10 -> 3 [penwidth="1", color="#aaaaaa", style="solid", label="[e1]"];
10 -> 7 [penwidth="1", color="#aaaaaa", style="solid", label="[b, c]"];
10 -> 9 [penwidth="1", color="#aaaaaa", style="solid", label="[c]"];
11 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[e1, b, c]"];
11 -> 2 [penwidth="1", color="#aaaaaa", style="solid", label="[e1, c]"];
11 -> 8 [penwidth="1", color="#aaaaaa", style="solid", label="[e1]"];
11 -> 4 [penwidth="1", color="#aaaaaa", style="solid", label="[b, c]"];
11 -> 5 [penwidth="1", color="#aaaaaa", style="solid", label="[c]"];
}
\ No newline at end of file
/*
* CCSL specification
* @author: jdeanton
* date : Thu August 30 2018 06:31:44 CEST
*/
ClockConstraintSystem modelCheckingProblem {
imports {
// import statements
import "platform:/plugin/fr.inria.aoste.timesquare.ccslkernel.model/ccsllibrary/kernel.ccslLib" as lib0;
import "platform:/plugin/fr.inria.aoste.timesquare.ccslkernel.model/ccsllibrary/CCSL.ccslLib" as lib1;
}
entryBlock main
Block main {
Clock a
Clock b
Clock c
Relation relation_0[Alternates]( AlternatesLeftClock-> a , AlternatesRightClock-> b )
// Expression cExpr=Periodic( PeriodicBaseClock -> b ,PeriodicPeriod -> two ,PeriodicOffset -> zero )
// Relation relation_1[Coincides]( Clock2 -> cExpr , Clock1 -> c )
Relation relation_1[SubClock]( LeftClock -> c , RightClock ->b )
}
}
digraph {
rankdir=LR;
start=0;
node [style="filled"]
0 [fillcolor="#ffffff", size="5", shape="circle", fontcolor="grey", label="0"];
1 [fillcolor="#ffffff", size="5", shape="circle", fontcolor="grey", label="1"];
2 [fillcolor="#ffffff", size="5", shape="circle", fontcolor="grey", label="2"];
0 -> 1 [penwidth="1", color="#111111", style="solid", label="a"];
1 -> 2 [penwidth="1", color="#111111", style="solid", label="b.c"];
1 -> 2 [penwidth="1", color="#111111", style="solid", label="b"];
2 -> 1 [penwidth="1", color="#111111", style="solid", label="a"];
}
......@@ -17,26 +17,36 @@ ClockConstraintSystem inhibitor {
Clock out_p
Clock in_t
Clock void_pplusone
Clock void_p
Clock unvoid_p
Expression void_expr2=DelayFor( DelayForClockToDelay -> void_pplusone ,DelayForClockForCounting -> void_pplusone ,DelayForDelay -> one )
Relation coinc0[Coincides](Clock2 -> void_expr2, Clock1 -> void_p )
Expression firstIn_p = Wait(WaitingClock -> in_p, WaitingValue -> one);
Expression firstVoid_pplusone = Wait(WaitingClock -> void_pplusone, WaitingValue -> one);
Relation relation_0[Precedes]( LeftClock -> firstVoid_pplusone , RightClock -> firstIn_p )
Expression in_p_minus_first=DelayFor(
DelayForClockForCounting -> in_p,
DelayForClockToDelay -> in_p,
DelayForDelay -> one
)
Expression in_p_minust_first_Inf_out_p=Inf(Clock1 -> in_p_minus_first, Clock2 -> out_p)
Expression unvoid_expr=Intersection(Clock1 -> out_p, Clock2 -> in_p_minust_first_Inf_out_p )
Relation coinc1[Coincides](Clock2 -> unvoid_expr, Clock1 -> unvoid_p )
Expression void_expr=Intersection(Clock1 -> out_p, Clock2 -> in_p_minust_first_Inf_out_p )
Relation coinc1[Coincides](Clock2 -> void_expr, Clock1 -> void_p )
Expression void_expr=SampledOn(SampledOnSampledClock -> unvoid_p, SampledOnTrigger -> in_p )
Relation coinc2[Coincides](Clock2 -> void_p, Clock1 -> void_expr )
Expression unvoid_expr=SampledOn(SampledOnSampledClock -> void_pplusone, SampledOnTrigger -> in_p )
Relation coinc2[Coincides](Clock2 -> unvoid_p, Clock1 -> unvoid_expr )
Expression void_union_unvoid=Union(Clock1 -> unvoid_p, Clock2 -> void_p)
Expression in_t_sampledOn_void_union_unvoid=SampledOn(SampledOnSampledClock -> in_t, SampledOnTrigger -> void_union_unvoid )
Expression in_t_sampledOn_void=SampledOn(SampledOnSampledClock ->in_t, SampledOnTrigger -> void_p )
Relation coinc3[Coincides](Clock2 -> in_t_sampledOn_void, Clock1 -> in_t_sampledOn_void_union_unvoid)
Expression in_t_sampledOn_unvoid=SampledOn(SampledOnSampledClock ->in_t, SampledOnTrigger -> unvoid_p )
Relation coinc3[Coincides](Clock2 -> in_t_sampledOn_unvoid, Clock1 -> in_t_sampledOn_void_union_unvoid)
Relation excl1[Exclusion](Clock2 -> in_p, Clock1 -> out_p )
Relation Prec1[Precedes](LeftClock -> in_p, RightClock -> out_p)
......
digraph {
rankdir=LR;
start=0;
node [style="filled"]
0 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="0"];
1 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="1"];
2 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="2"];
3 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="3"];
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5 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="5"];
6 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="6"];
7 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="7"];
8 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="8"];
9 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="9"];
10 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="10"];
11 [fillcolor="#ffffff", size="10", shape="circle", fontcolor="black", label="11"];
0 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[in_t]"];
0 -> 2 [penwidth="2", color="#aa0000", style="solid", label="[in_p]"];
1 -> 1 [penwidth="1", color="#aaaaaa", style="solid", label="[in_t]"];
1 -> 3 [penwidth="1", color="#aaaaaa", style="solid", label="[in_p]"];
2 -> 4 [penwidth="2", color="#aa0000", style="solid", label="[out_p, void_p]"];
2 -> 3 [penwidth="1", color="#aaaaaa", style="solid", label="[in_t]"];
2 -> 5 [penwidth="2", color="#aa0000", style="solid", label="[in_p]"];
3 -> 3 [penwidth="1", color="#aaaaaa", style="solid", label="[in_t]"];
3 -> 6 [penwidth="1", color="#aaaaaa", style="solid", label="[in_p]"];
4 -> 7 [penwidth="2", color="#aa0000", style="solid", label="[in_t]"];
4 -> 8 [penwidth="2", color="#aa0000", style="solid", label="[unvoid_p, in_p]"];
5 -> 8 [penwidth="2", color="#aa0000", style="solid", label="[out_p]"];
5 -> 6 [penwidth="1", color="#aaaaaa", style="solid", label="[in_t]"];
6 -> 9 [penwidth="1", color="#aaaaaa", style="solid", label="[out_p]"];
6 -> 6 [penwidth="1", color="#aaaaaa", style="solid", label="[in_t]"];
7 -> 7 [penwidth="2", color="#aa0000", style="solid", label="[in_t]"];
7 -> 8 [penwidth="2", color="#aa0000", style="solid", label="[unvoid_p, in_p]"];
8 -> 10 [penwidth="2", color="#aa0000", style="solid", label="[out_p, void_p]"];
8 -> 9 [penwidth="1", color="#aaaaaa", style="solid", label="[in_t]"];
8 -> 5 [penwidth="2", color="#aa0000", style="solid", label="[in_p]"];
9 -> 9 [penwidth="1", color="#aaaaaa", style="solid", label="[in_t]"];
9 -> 6 [penwidth="1", color="#aaaaaa", style="solid", label="[in_p]"];
10 -> 11 [penwidth="2", color="#aa0000", style="solid", label="[in_t]"];
10 -> 8 [penwidth="2", color="#aa0000", style="solid", label="[unvoid_p, in_p]"];
11 -> 11 [penwidth="2", color="#aa0000", style="solid", label="[in_t]"];
11 -> 8 [penwidth="2", color="#aa0000", style="solid", label="[unvoid_p, in_p]"];
}
/*
* CCSL specification
* @author: jdeanton
* date : Fri November 27 2015 04:33:30 CET
*/
ClockConstraintSystem inhibitor {
imports {
// import statements
import "platform:/plugin/fr.inria.aoste.timesquare.ccslkernel.model/ccsllibrary/kernel.ccslLib" as lib0;
import "platform:/plugin/fr.inria.aoste.timesquare.ccslkernel.model/ccsllibrary/CCSL.ccslLib" as lib1;
}
entryBlock main
Block main {
Expression in_p_minus_first=DelayFor(
DelayForClockForCounting -> in_p,
DelayForClockToDelay -> in_p,
DelayForDelay -> one
)
Expression in_p_minust_first_Inf_out_p=Inf(Clock1 -> in_p_minus_first, Clock2 -> out_p)
Expression unvoid_expr=Intersection(Clock1 -> out_p, Clock2 -> in_p_minust_first_Inf_out_p )
Expression void_expr=SampledOn(SampledOnSampledClock -> unvoid_p, SampledOnTrigger -> in_p )
Expression void_union_unvoid=Union(Clock1 -> unvoid_p, Clock2 -> void_p)
Expression in_t_sampledOn_void_union_unvoid=SampledOn(SampledOnSampledClock -> in_t, SampledOnTrigger -> void_union_unvoid )
Expression in_t_sampledOn_void=SampledOn(SampledOnSampledClock ->in_t, SampledOnTrigger -> void_p )
//make it bounded
Expression in_p_delayedFor2=DelayFor(
DelayForClockToDelay -> in_p,
DelayForClockForCounting -> in_p,
DelayForDelay -> two
)
Relation coinc1[Coincides](Clock2 -> unvoid_expr, Clock1 -> unvoid_p )
Relation coinc2[Coincides](Clock2 -> void_p, Clock1 -> void_expr )
Relation coinc3[Coincides](Clock2 -> in_t_sampledOn_void, Clock1 -> in_t_sampledOn_void_union_unvoid)
Relation excl1[Exclusion](Clock2 -> in_p, Clock1 -> out_p )
Relation Prec1[Precedes](LeftClock -> in_p, RightClock -> out_p)
Relation excl2[Exclusion](Clock2 -> in_t, Clock1 -> out_p)
Relation excl3[Exclusion](Clock2 -> in_t, Clock1 -> in_p)
Relation Prec2[Precedes](LeftClock -> out_p, RightClock -> in_p_delayedFor2 )
Clock in_p
Clock out_p
Clock in_t
Clock void_p
Clock unvoid_p
}
}
\ No newline at end of file
$date
Mon Jul 30 15:30:24 CEST 2018
$end
$version
VCD Generation 2.1.0
$end
$comment alias inhibitor__main__in_p "inhibitor::main::in_p" $end
$comment alias inhibitor__main__in_p_delayedFor2 "inhibitor::main::in_p_delayedFor2" $end
$comment hide inhibitor__main__in_p_delayedFor2__DelayForDef__DelayFor_defer $end
$comment alias inhibitor__main__in_p_delayedFor2__DelayForDef__DelayFor_defer "inhibitor::main::in_p_delayedFor2::DelayForDef::DelayFor_defer" $end
$comment alias inhibitor__main__in_p_minus_first "inhibitor::main::in_p_minus_first" $end
$comment hide inhibitor__main__in_p_minus_first__DelayForDef__DelayFor_defer $end
$comment alias inhibitor__main__in_p_minus_first__DelayForDef__DelayFor_defer "inhibitor::main::in_p_minus_first::DelayForDef::DelayFor_defer" $end
$comment alias inhibitor__main__in_p_minust_first_Inf_out_p "inhibitor::main::in_p_minust_first_Inf_out_p" $end
$comment alias inhibitor__main__in_t "inhibitor::main::in_t" $end
$comment alias inhibitor__main__in_t_sampledOn_void "inhibitor::main::in_t_sampledOn_void" $end
$comment hide inhibitor__main__in_t_sampledOn_void__SampledOnDef__OneSampled $end
$comment alias inhibitor__main__in_t_sampledOn_void__SampledOnDef__OneSampled "inhibitor::main::in_t_sampledOn_void::SampledOnDef::OneSampled" $end
$comment hide inhibitor__main__in_t_sampledOn_void__SampledOnDef__SampledOnrootConcat $end
$comment alias inhibitor__main__in_t_sampledOn_void__SampledOnDef__SampledOnrootConcat "inhibitor::main::in_t_sampledOn_void::SampledOnDef::SampledOnrootConcat" $end
$comment alias inhibitor__main__in_t_sampledOn_void_union_unvoid "inhibitor::main::in_t_sampledOn_void_union_unvoid" $end
$comment hide inhibitor__main__in_t_sampledOn_void_union_unvoid__SampledOnDef__OneSampled $end
$comment alias inhibitor__main__in_t_sampledOn_void_union_unvoid__SampledOnDef__OneSampled "inhibitor::main::in_t_sampledOn_void_union_unvoid::SampledOnDef::OneSampled" $end
$comment hide inhibitor__main__in_t_sampledOn_void_union_unvoid__SampledOnDef__SampledOnrootConcat $end
$comment alias inhibitor__main__in_t_sampledOn_void_union_unvoid__SampledOnDef__SampledOnrootConcat "inhibitor::main::in_t_sampledOn_void_union_unvoid::SampledOnDef::SampledOnrootConcat" $end
$comment alias inhibitor__main__out_p "inhibitor::main::out_p" $end
$comment alias inhibitor__main__unvoid_expr "inhibitor::main::unvoid_expr" $end
$comment alias inhibitor__main__unvoid_p "inhibitor::main::unvoid_p" $end
$comment alias inhibitor__main__void_expr "inhibitor::main::void_expr" $end
$comment hide inhibitor__main__void_expr__SampledOnDef__OneSampled $end
$comment alias inhibitor__main__void_expr__SampledOnDef__OneSampled "inhibitor::main::void_expr::SampledOnDef::OneSampled" $end
$comment hide inhibitor__main__void_expr__SampledOnDef__SampledOnrootConcat $end
$comment alias inhibitor__main__void_expr__SampledOnDef__SampledOnrootConcat "inhibitor::main::void_expr::SampledOnDef::SampledOnrootConcat" $end
$comment alias inhibitor__main__void_p "inhibitor::main::void_p" $end
$comment alias inhibitor__main__void_union_unvoid "inhibitor::main::void_union_unvoid" $end
$comment scale 0.1 $end
$comment relation "inhibitor2018_0730_153023.ccslrelationmodel" $end
$comment xmi inhibitor__main__in_t "inhibitor2018_0730_153023.trace#//@references.0" $end
$comment xmi inhibitor__main__in_p "inhibitor2018_0730_153023.trace#//@references.1" $end
$comment xmi inhibitor__main__void_p "inhibitor2018_0730_153023.trace#//@references.2" $end
$comment xmi inhibitor__main__out_p "inhibitor2018_0730_153023.trace#//@references.3" $end
$comment xmi inhibitor__main__unvoid_p "inhibitor2018_0730_153023.trace#//@references.4" $end
$comment xmi inhibitor__main__in_t_sampledOn_void__SampledOnDef__OneSampled "inhibitor2018_0730_153023.trace#//@references.5" $end
$comment xmi inhibitor__main__void_expr "inhibitor2018_0730_153023.trace#//@references.6" $end
$comment xmi inhibitor__main__in_p_delayedFor2 "inhibitor2018_0730_153023.trace#//@references.7" $end
$comment xmi inhibitor__main__in_p_minust_first_Inf_out_p "inhibitor2018_0730_153023.trace#//@references.8" $end
$comment xmi inhibitor__main__in_p_minus_first "inhibitor2018_0730_153023.trace#//@references.9" $end
$comment xmi inhibitor__main__unvoid_expr "inhibitor2018_0730_153023.trace#//@references.10" $end
$comment xmi inhibitor__main__void_expr__SampledOnDef__SampledOnrootConcat "inhibitor2018_0730_153023.trace#//@references.11" $end
$comment xmi inhibitor__main__in_p_minus_first__DelayForDef__DelayFor_defer "inhibitor2018_0730_153023.trace#//@references.12" $end
$comment xmi inhibitor__main__in_t_sampledOn_void_union_unvoid "inhibitor2018_0730_153023.trace#//@references.13" $end
$comment xmi inhibitor__main__in_t_sampledOn_void_union_unvoid__SampledOnDef__SampledOnrootConcat "inhibitor2018_0730_153023.trace#//@references.14" $end
$comment xmi inhibitor__main__in_t_sampledOn_void "inhibitor2018_0730_153023.trace#//@references.15" $end
$comment xmi inhibitor__main__void_union_unvoid "inhibitor2018_0730_153023.trace#//@references.16" $end
$comment xmi inhibitor__main__in_t_sampledOn_void_union_unvoid__SampledOnDef__OneSampled "inhibitor2018_0730_153023.trace#//@references.17" $end
$comment xmi inhibitor__main__in_p_delayedFor2__DelayForDef__DelayFor_defer "inhibitor2018_0730_153023.trace#//@references.18" $end
$comment xmi inhibitor__main__void_expr__SampledOnDef__OneSampled "inhibitor2018_0730_153023.trace#//@references.19" $end
$comment xmi inhibitor__main__in_t_sampledOn_void__SampledOnDef__SampledOnrootConcat "inhibitor2018_0730_153023.trace#//@references.20" $end
$scope module top $end
$var event 1 !1 inhibitor__main__in_p $end
$var event 1 !2 inhibitor__main__in_p_delayedFor2 $end
$var event 1 !3 inhibitor__main__in_p_delayedFor2__DelayForDef__DelayFor_defer $end
$var event 1 !4 inhibitor__main__in_p_minus_first $end
$var event 1 !5 inhibitor__main__in_p_minus_first__DelayForDef__DelayFor_defer $end
$var event 1 !6 inhibitor__main__in_p_minust_first_Inf_out_p $end
$var event 1 !7 inhibitor__main__in_t $end
$var event 1 !8 inhibitor__main__in_t_sampledOn_void $end
$var event 1 !9 inhibitor__main__in_t_sampledOn_void__SampledOnDef__OneSampled $end
$var event 1 !10 inhibitor__main__in_t_sampledOn_void__SampledOnDef__SampledOnrootConcat $end
$var event 1 !11 inhibitor__main__in_t_sampledOn_void_union_unvoid $end
$var event 1 !12 inhibitor__main__in_t_sampledOn_void_union_unvoid__SampledOnDef__OneSampled $end
$var event 1 !13 inhibitor__main__in_t_sampledOn_void_union_unvoid__SampledOnDef__SampledOnrootConcat $end
$var event 1 !14 inhibitor__main__out_p $end
$var event 1 !15 inhibitor__main__unvoid_expr $end
$var event 1 !16 inhibitor__main__unvoid_p $end
$var event 1 !17 inhibitor__main__void_expr $end
$var event 1 !18 inhibitor__main__void_expr__SampledOnDef__OneSampled $end
$var event 1 !19 inhibitor__main__void_expr__SampledOnDef__SampledOnrootConcat $end
$var event 1 !20 inhibitor__main__void_p $end
$var event 1 !21 inhibitor__main__void_union_unvoid $end
$upscope $end
$enddefinitions $end
#0
1!1
#10
1!7
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1!7
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1!1
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#40
1!14
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1!7
#60
1!1
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#70
1!14
#80
1!1
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1!6
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#90
1!7
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1!7
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1!7
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1!1
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#160
1!7
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1!7
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1!7
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1!14
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1!1
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#230
1!14
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1!7
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1!7
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1!1
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#270
1!14
#280
1!1
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1!6
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1!5
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#290
1!14
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1!7
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1!7
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1!1
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#350
1!14
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1!7
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1!1
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#380
1!14