From fb823f5341f38337fed74de731417bd1cb400b69 Mon Sep 17 00:00:00 2001
From: Pierre Jacquot <pierre.jacquot@inria.fr>
Date: Tue, 20 May 2025 09:26:20 +0200
Subject: [PATCH] [strasbourg][fleckenstein] update CPU microcode
---
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.yaml | 2 +-
20 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.json
index 44997fb2c39..57cc3f1b93a 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.json
@@ -296,7 +296,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake-SP",
- "microcode": "0xd0003e7",
+ "microcode": "0xd000404",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.json
index b233fa894ad..09055994d05 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.json
@@ -296,7 +296,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake-SP",
- "microcode": "0xd0003e7",
+ "microcode": "0xd000404",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.json
index a4f90656021..8a2af773cee 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.json
@@ -296,7 +296,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake-SP",
- "microcode": "0xd0003e7",
+ "microcode": "0xd000404",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.json
index 5feaf445efe..88910e72712 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.json
@@ -296,7 +296,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake-SP",
- "microcode": "0xd0003e7",
+ "microcode": "0xd000404",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.json
index 199571f79c8..7aba75cbd6a 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.json
@@ -296,7 +296,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake-SP",
- "microcode": "0xd0003b9",
+ "microcode": "0xd000404",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.json
index 6d5b316f9e3..aeb0342b753 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.json
@@ -296,7 +296,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake-SP",
- "microcode": "0xd0003e7",
+ "microcode": "0xd000404",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.json
index 711e1b6e28d..9f97d0b8b46 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.json
@@ -296,7 +296,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake-SP",
- "microcode": "0xd0003e7",
+ "microcode": "0xd000404",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.json
index 6af3078bc3f..c1fbf05b88b 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.json
@@ -296,7 +296,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake-SP",
- "microcode": "0xd0003e7",
+ "microcode": "0xd000404",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.json
index 12cbef8c072..0bd39869dc4 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.json
@@ -296,7 +296,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake-SP",
- "microcode": "0xd0003e7",
+ "microcode": "0xd000404",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.json
index fba56b30d83..bc878e44ecf 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.json
@@ -296,7 +296,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake-SP",
- "microcode": "0xd0003e7",
+ "microcode": "0xd000404",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.yaml
index 70ba0de9612..945e70fd422 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.yaml
@@ -177,7 +177,7 @@ fleckenstein-1:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003e7'
+ microcode: '0xd000404'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.yaml
index 02e09eaf23a..25e00200cbb 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.yaml
@@ -177,7 +177,7 @@ fleckenstein-10:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003e7'
+ microcode: '0xd000404'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.yaml
index 0bd5878db74..daa18d12b19 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.yaml
@@ -177,7 +177,7 @@ fleckenstein-2:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003e7'
+ microcode: '0xd000404'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.yaml
index 3e87f00652c..257d782d7b3 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.yaml
@@ -177,7 +177,7 @@ fleckenstein-3:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003e7'
+ microcode: '0xd000404'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.yaml
index e053577fa89..7f54a7560f7 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.yaml
@@ -177,7 +177,7 @@ fleckenstein-4:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003b9'
+ microcode: '0xd000404'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.yaml
index 972fb9e6500..aa19998fa39 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.yaml
@@ -177,7 +177,7 @@ fleckenstein-5:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003e7'
+ microcode: '0xd000404'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.yaml
index bb800879e08..fa3bc8f41b0 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.yaml
@@ -177,7 +177,7 @@ fleckenstein-6:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003e7'
+ microcode: '0xd000404'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.yaml
index ba190c8dd86..083b6dc999d 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.yaml
@@ -177,7 +177,7 @@ fleckenstein-7:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003e7'
+ microcode: '0xd000404'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.yaml
index 6681647bd7b..1cd65376463 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.yaml
@@ -177,7 +177,7 @@ fleckenstein-8:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003e7'
+ microcode: '0xd000404'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.yaml
index bd975433f82..09fba3911e9 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.yaml
@@ -177,7 +177,7 @@ fleckenstein-9:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003e7'
+ microcode: '0xd000404'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
--
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