diff --git a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-1.json b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-1.json
index adf6d1c726fe9c93eadf0e82416b656998c81a02..898e0e954c91eb4b1965028f1bb415c0c95e8223 100644
--- a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-1.json
+++ b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-1.json
@@ -272,7 +272,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Ice Lake-SP",
-    "microcode": "0xd0003e7",
+    "microcode": "0xd0003f5",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz",
     "vendor": "Intel",
diff --git a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-2.json b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-2.json
index eda619ab3242154842f9ae7ddc6e6d2051b46121..a1485e95c3d0c192e026c91efd579ac10833ea32 100644
--- a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-2.json
+++ b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-2.json
@@ -272,7 +272,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Ice Lake-SP",
-    "microcode": "0xd0003e7",
+    "microcode": "0xd0003f5",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz",
     "vendor": "Intel",
diff --git a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-3.json b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-3.json
index dbd291862253f0398c685bfacc3dbd910ff3b21a..07d38e7d45b9d3590a13b844005d8cc15963270b 100644
--- a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-3.json
+++ b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-3.json
@@ -272,7 +272,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Ice Lake-SP",
-    "microcode": "0xd0003e7",
+    "microcode": "0xd0003f5",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz",
     "vendor": "Intel",
diff --git a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-4.json b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-4.json
index cb25f71d73c85158cccf1e8f6927cad2443048e8..260eaf2fda690f2c9d7a70323a345323a510e5d7 100644
--- a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-4.json
+++ b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-4.json
@@ -272,7 +272,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Ice Lake-SP",
-    "microcode": "0xd0003e7",
+    "microcode": "0xd0003f5",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz",
     "vendor": "Intel",
diff --git a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-5.json b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-5.json
index 23b5183c309a2b94e7f7cda603064f829808d0b3..7b17937e3d4a98710a2d3513c6c4982f8bab5c2f 100644
--- a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-5.json
+++ b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-5.json
@@ -272,7 +272,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Ice Lake-SP",
-    "microcode": "0xd0003e7",
+    "microcode": "0xd0003f5",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz",
     "vendor": "Intel",
diff --git a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-6.json b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-6.json
index 3ababd57818137c9c90858addc95260e0a94ebbe..4dfe63658434a34b94c869c9af7fa2bf61b0d063 100644
--- a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-6.json
+++ b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-6.json
@@ -272,7 +272,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Ice Lake-SP",
-    "microcode": "0xd0003e7",
+    "microcode": "0xd0003f5",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz",
     "vendor": "Intel",
diff --git a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-7.json b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-7.json
index 59362002a45e5b31c4d9c13756af4ef851d7a7a0..d8a9da1ce1f05197be99d8b1c56001898c91de2f 100644
--- a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-7.json
+++ b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-7.json
@@ -272,7 +272,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Ice Lake-SP",
-    "microcode": "0xd0003e7",
+    "microcode": "0xd0003f5",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz",
     "vendor": "Intel",
diff --git a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-8.json b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-8.json
index 16778710bb3e136775352d4feeea3844ab83c8c7..44c273fc04f2a0bae1131ac63a7e909fe76d5038 100644
--- a/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-8.json
+++ b/data/grid5000/sites/louvain/clusters/spirou/nodes/spirou-8.json
@@ -272,7 +272,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Ice Lake-SP",
-    "microcode": "0xd0003e7",
+    "microcode": "0xd0003f5",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz",
     "vendor": "Intel",
diff --git a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-1.yaml b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-1.yaml
index 17980344929604997bdbff2de146e3007353aed7..b56c67f222f78f696078e7532cc1443982e11a4d 100644
--- a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-1.yaml
+++ b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-1.yaml
@@ -170,7 +170,7 @@ spirou-1:
     cache_l3: 37748736
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0xd0003e7'
+    microcode: '0xd0003f5'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz
     vendor: Intel
diff --git a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-2.yaml b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-2.yaml
index 7b47b9419a20c4aaf3f46c29870172b5758fdc3c..bc579920b0ebf0bce228a0c7c17bb1975ffa5f9c 100644
--- a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-2.yaml
+++ b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-2.yaml
@@ -170,7 +170,7 @@ spirou-2:
     cache_l3: 37748736
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0xd0003e7'
+    microcode: '0xd0003f5'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz
     vendor: Intel
diff --git a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-3.yaml b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-3.yaml
index fc0098b8b232277969f55abf81762e45c52844ae..988937d8c21476a2750e955bed4488e550e9efcd 100644
--- a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-3.yaml
+++ b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-3.yaml
@@ -170,7 +170,7 @@ spirou-3:
     cache_l3: 37748736
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0xd0003e7'
+    microcode: '0xd0003f5'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz
     vendor: Intel
diff --git a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-4.yaml b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-4.yaml
index 7bae9fde31b6e429755c8c577712ea6571d60942..3a7d096bcf9452115f9a337d127bf5cb576bdf90 100644
--- a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-4.yaml
+++ b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-4.yaml
@@ -170,7 +170,7 @@ spirou-4:
     cache_l3: 37748736
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0xd0003e7'
+    microcode: '0xd0003f5'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz
     vendor: Intel
diff --git a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-5.yaml b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-5.yaml
index 0d498493ac5ecb5e3601e5c83eeba4fabb7cce88..90d3ec9253f02c3bcb8b7fb2fcdaab286401bb9a 100644
--- a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-5.yaml
+++ b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-5.yaml
@@ -170,7 +170,7 @@ spirou-5:
     cache_l3: 37748736
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0xd0003e7'
+    microcode: '0xd0003f5'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz
     vendor: Intel
diff --git a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-6.yaml b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-6.yaml
index b7c07b17f69e98801ad95f8f55d2b897a4d82c8c..800946c60be3e7bbe55f54c7b6e2ef35c17c236b 100644
--- a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-6.yaml
+++ b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-6.yaml
@@ -170,7 +170,7 @@ spirou-6:
     cache_l3: 37748736
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0xd0003e7'
+    microcode: '0xd0003f5'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz
     vendor: Intel
diff --git a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-7.yaml b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-7.yaml
index a3911e88cc399d16ebd0b67c8ec63e284d43a5cd..d6c16626feee78673497c9c1df315da93db7f6bf 100644
--- a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-7.yaml
+++ b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-7.yaml
@@ -170,7 +170,7 @@ spirou-7:
     cache_l3: 37748736
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0xd0003e7'
+    microcode: '0xd0003f5'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz
     vendor: Intel
diff --git a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-8.yaml b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-8.yaml
index a2482484951e51b7b2e2a3d150aa66614fb99967..174df8965eea5adb97757123266570a80b12c043 100644
--- a/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-8.yaml
+++ b/input/grid5000/sites/louvain/clusters/spirou/nodes/spirou-8.yaml
@@ -170,7 +170,7 @@ spirou-8:
     cache_l3: 37748736
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0xd0003e7'
+    microcode: '0xd0003f5'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 5318Y CPU @ 2.10GHz
     vendor: Intel