From de7cba91c6e763285307fed141c7c6d1a2ec0520 Mon Sep 17 00:00:00 2001
From: Samir Noir <samir.noir@inria.fr>
Date: Mon, 18 Nov 2019 15:56:41 +0100
Subject: [PATCH] [nancy] update chifflot cpu microcode version

---
 .../sites/lille/clusters/chifflot/nodes/chifflot-1.json         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-2.json         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-3.json         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-4.json         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-5.json         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-6.json         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-7.json         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-8.json         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-1.yaml         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-2.yaml         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-3.yaml         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-4.yaml         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-5.yaml         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-6.yaml         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-7.yaml         | 2 +-
 .../sites/lille/clusters/chifflot/nodes/chifflot-8.yaml         | 2 +-
 16 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-1.json b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-1.json
index cd188ef307e..e5f3c53b1a1 100644
--- a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-1.json
+++ b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-1.json
@@ -220,7 +220,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Skylake",
-    "microcode": "0x200005e",
+    "microcode": "0x2000065",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz",
     "vendor": "Intel",
diff --git a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-2.json b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-2.json
index 786c9e1c37b..40af6dd10c8 100644
--- a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-2.json
+++ b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-2.json
@@ -220,7 +220,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Skylake",
-    "microcode": "0x200005e",
+    "microcode": "0x2000065",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz",
     "vendor": "Intel",
diff --git a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-3.json b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-3.json
index 677ae79d0a3..7be1689925b 100644
--- a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-3.json
+++ b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-3.json
@@ -220,7 +220,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Skylake",
-    "microcode": "0x200005e",
+    "microcode": "0x2000065",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz",
     "vendor": "Intel",
diff --git a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-4.json b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-4.json
index ba78d3f5bc1..705783b4ff3 100644
--- a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-4.json
+++ b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-4.json
@@ -220,7 +220,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Skylake",
-    "microcode": "0x200005e",
+    "microcode": "0x2000065",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz",
     "vendor": "Intel",
diff --git a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-5.json b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-5.json
index 1967d9d499f..89b3bc37057 100644
--- a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-5.json
+++ b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-5.json
@@ -220,7 +220,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Skylake",
-    "microcode": "0x200005e",
+    "microcode": "0x2000065",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz",
     "vendor": "Intel",
diff --git a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-6.json b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-6.json
index 39f27105fe0..657e7089ff5 100644
--- a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-6.json
+++ b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-6.json
@@ -220,7 +220,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Skylake",
-    "microcode": "0x200005e",
+    "microcode": "0x2000065",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz",
     "vendor": "Intel",
diff --git a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-7.json b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-7.json
index 5d9bd4e32ba..e45592cd4aa 100644
--- a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-7.json
+++ b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-7.json
@@ -220,7 +220,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Skylake",
-    "microcode": "0x200005e",
+    "microcode": "0x2000065",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz",
     "vendor": "Intel",
diff --git a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-8.json b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-8.json
index 1e3b320ab3e..99223178789 100644
--- a/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-8.json
+++ b/data/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-8.json
@@ -220,7 +220,7 @@
     "ht_capable": true,
     "instruction_set": "x86-64",
     "microarchitecture": "Skylake",
-    "microcode": "0x200005e",
+    "microcode": "0x2000065",
     "model": "Intel Xeon",
     "other_description": "Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz",
     "vendor": "Intel",
diff --git a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-1.yaml b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-1.yaml
index 8ae2dd49eb3..63efb3ea726 100644
--- a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-1.yaml
+++ b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-1.yaml
@@ -112,7 +112,7 @@ chifflot-1:
     clock_speed: 2600000000
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0x200005e'
+    microcode: '0x2000065'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz
     vendor: Intel
diff --git a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-2.yaml b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-2.yaml
index 7ee3986ceb6..122247fe36e 100644
--- a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-2.yaml
+++ b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-2.yaml
@@ -112,7 +112,7 @@ chifflot-2:
     clock_speed: 2600000000
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0x200005e'
+    microcode: '0x2000065'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz
     vendor: Intel
diff --git a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-3.yaml b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-3.yaml
index 0379aad3c24..6d717e7360d 100644
--- a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-3.yaml
+++ b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-3.yaml
@@ -112,7 +112,7 @@ chifflot-3:
     clock_speed: 2600000000
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0x200005e'
+    microcode: '0x2000065'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz
     vendor: Intel
diff --git a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-4.yaml b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-4.yaml
index 1ec3b4d6d97..0218d175294 100644
--- a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-4.yaml
+++ b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-4.yaml
@@ -112,7 +112,7 @@ chifflot-4:
     clock_speed: 2600000000
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0x200005e'
+    microcode: '0x2000065'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz
     vendor: Intel
diff --git a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-5.yaml b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-5.yaml
index 0daaf5ae834..6e091e25187 100644
--- a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-5.yaml
+++ b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-5.yaml
@@ -112,7 +112,7 @@ chifflot-5:
     clock_speed: 2600000000
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0x200005e'
+    microcode: '0x2000065'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz
     vendor: Intel
diff --git a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-6.yaml b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-6.yaml
index 08c64b227c5..625a7e347c3 100644
--- a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-6.yaml
+++ b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-6.yaml
@@ -112,7 +112,7 @@ chifflot-6:
     clock_speed: 2600000000
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0x200005e'
+    microcode: '0x2000065'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz
     vendor: Intel
diff --git a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-7.yaml b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-7.yaml
index 56401c2af95..70db99bcd9f 100644
--- a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-7.yaml
+++ b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-7.yaml
@@ -112,7 +112,7 @@ chifflot-7:
     clock_speed: 2600000000
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0x200005e'
+    microcode: '0x2000065'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz
     vendor: Intel
diff --git a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-8.yaml b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-8.yaml
index ee6f58c1d64..4e97026cdc7 100644
--- a/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-8.yaml
+++ b/input/grid5000/sites/lille/clusters/chifflot/nodes/chifflot-8.yaml
@@ -112,7 +112,7 @@ chifflot-8:
     clock_speed: 2600000000
     ht_capable: true
     instruction_set: x86-64
-    microcode: '0x200005e'
+    microcode: '0x2000065'
     model: Intel Xeon
     other_description: Intel(R) Xeon(R) Gold 6126 CPU @ 2.60GHz
     vendor: Intel
-- 
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