Commit 712db187 authored by LOUP David's avatar LOUP David
Browse files

[edel] Update cpu freq for some edel

parent 010f850c
......@@ -149,7 +149,7 @@
"cache_l1i": 32768,
"cache_l2": 262144,
"cache_l3": 8388608,
"clock_speed": 2250000000,
"clock_speed": 2300000000,
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Nehalem",
......
......@@ -149,7 +149,7 @@
"cache_l1i": 32768,
"cache_l2": 262144,
"cache_l3": 8388608,
"clock_speed": 2250000000,
"clock_speed": 2300000000,
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Nehalem",
......
......@@ -149,7 +149,7 @@
"cache_l1i": 32768,
"cache_l2": 262144,
"cache_l3": 8388608,
"clock_speed": 2250000000,
"clock_speed": 2300000000,
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Nehalem",
......
......@@ -149,7 +149,7 @@
"cache_l1i": 32768,
"cache_l2": 262144,
"cache_l3": 8388608,
"clock_speed": 2250000000,
"clock_speed": 2300000000,
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Nehalem",
......
......@@ -10104,7 +10104,7 @@
"cache_l1i": 32768,
"cache_l2": 262144,
"cache_l3": 8388608,
"clock_speed": 2250000000,
"clock_speed": 2300000000,
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Nehalem",
......@@ -10303,7 +10303,7 @@
"cache_l1i": 32768,
"cache_l2": 262144,
"cache_l3": 8388608,
"clock_speed": 2250000000,
"clock_speed": 2300000000,
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Nehalem",
......@@ -10502,7 +10502,7 @@
"cache_l1i": 32768,
"cache_l2": 262144,
"cache_l3": 8388608,
"clock_speed": 2250000000,
"clock_speed": 2300000000,
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Nehalem",
......@@ -12250,7 +12250,7 @@
"cache_l1i": 32768,
"cache_l2": 262144,
"cache_l3": 8388608,
"clock_speed": 2250000000,
"clock_speed": 2300000000,
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Nehalem",
......@@ -71,7 +71,7 @@ edel-55:
cache_l1i: 32768
cache_l2: 262144
cache_l3: 8388608
clock_speed: 2250000000
clock_speed: 2300000000
ht_capable: true
instruction_set: x86-64
model: Intel Xeon
......
......@@ -71,7 +71,7 @@ edel-56:
cache_l1i: 32768
cache_l2: 262144
cache_l3: 8388608
clock_speed: 2250000000
clock_speed: 2300000000
ht_capable: true
instruction_set: x86-64
model: Intel Xeon
......
......@@ -71,7 +71,7 @@ edel-57:
cache_l1i: 32768
cache_l2: 262144
cache_l3: 8388608
clock_speed: 2250000000
clock_speed: 2300000000
ht_capable: true
instruction_set: x86-64
model: Intel Xeon
......
......@@ -71,7 +71,7 @@ edel-65:
cache_l1i: 32768
cache_l2: 262144
cache_l3: 8388608
clock_speed: 2250000000
clock_speed: 2300000000
ht_capable: true
instruction_set: x86-64
model: Intel Xeon
......
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