From 334de28437b8979d6668622063507786ea98ed7d Mon Sep 17 00:00:00 2001
From: Pierre Jacquot <pierre.jacquot@inria.fr>
Date: Wed, 15 May 2024 18:10:14 +0200
Subject: [PATCH] [strasbourg][fleckenstein] Update CPU microcode
---
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.json | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.yaml | 2 +-
.../strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.yaml | 2 +-
20 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.json
index 9fd1ac19f07..35c3b5c865b 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.json
@@ -258,7 +258,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake",
- "microcode": "0xd0003a5",
+ "microcode": "0xd0003b9",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.json
index 56e66c59db4..45a809a0162 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.json
@@ -258,7 +258,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake",
- "microcode": "0xd0003a5",
+ "microcode": "0xd0003b9",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.json
index fc2314a0e82..1663ba5e2c6 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.json
@@ -258,7 +258,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake",
- "microcode": "0xd0003a5",
+ "microcode": "0xd0003b9",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.json
index 3e9f92dd69b..d40eb4f63ac 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.json
@@ -258,7 +258,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake",
- "microcode": "0xd0003a5",
+ "microcode": "0xd0003b9",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.json
index df94c956137..e096a6c9d9f 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.json
@@ -258,7 +258,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake",
- "microcode": "0xd0003a5",
+ "microcode": "0xd0003b9",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.json
index 218660c8738..b148a812bc6 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.json
@@ -258,7 +258,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake",
- "microcode": "0xd0003a5",
+ "microcode": "0xd0003b9",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.json
index 9530ff590ae..792206e223f 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.json
@@ -258,7 +258,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake",
- "microcode": "0xd0003a5",
+ "microcode": "0xd0003b9",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.json
index 65c04d40347..db6730452ac 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.json
@@ -258,7 +258,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake",
- "microcode": "0xd0003a5",
+ "microcode": "0xd0003b9",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.json
index e103c356e78..4cae171c700 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.json
@@ -258,7 +258,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake",
- "microcode": "0xd0003a5",
+ "microcode": "0xd0003b9",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.json b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.json
index e592e9ce0b2..6a6437b3c30 100644
--- a/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.json
+++ b/data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.json
@@ -258,7 +258,7 @@
"ht_capable": true,
"instruction_set": "x86-64",
"microarchitecture": "Ice Lake",
- "microcode": "0xd0003a5",
+ "microcode": "0xd0003b9",
"model": "Intel Xeon",
"other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
"vendor": "Intel",
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.yaml
index 63e8ae4a593..ada63f8fbd3 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.yaml
@@ -156,7 +156,7 @@ fleckenstein-1:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003a5'
+ microcode: '0xd0003b9'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.yaml
index 519f0171a6d..f2dada96e1c 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.yaml
@@ -156,7 +156,7 @@ fleckenstein-10:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003a5'
+ microcode: '0xd0003b9'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.yaml
index 02178c8d9d1..9386522a22c 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.yaml
@@ -156,7 +156,7 @@ fleckenstein-2:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003a5'
+ microcode: '0xd0003b9'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.yaml
index caf681e1454..f1cbcfff70c 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.yaml
@@ -156,7 +156,7 @@ fleckenstein-3:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003a5'
+ microcode: '0xd0003b9'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.yaml
index 0106c70067a..321e0f8feb6 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.yaml
@@ -156,7 +156,7 @@ fleckenstein-4:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003a5'
+ microcode: '0xd0003b9'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.yaml
index f28a102d51c..fba155fe06d 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.yaml
@@ -156,7 +156,7 @@ fleckenstein-5:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003a5'
+ microcode: '0xd0003b9'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.yaml
index bf0b5b3f4f0..53dc4b21b8e 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.yaml
@@ -156,7 +156,7 @@ fleckenstein-6:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003a5'
+ microcode: '0xd0003b9'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.yaml
index 91ed94251cd..601ba1f38db 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.yaml
@@ -156,7 +156,7 @@ fleckenstein-7:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003a5'
+ microcode: '0xd0003b9'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.yaml
index 6a0f4c4b23e..5f482d6063c 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.yaml
@@ -156,7 +156,7 @@ fleckenstein-8:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003a5'
+ microcode: '0xd0003b9'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
diff --git a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.yaml b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.yaml
index f45948c0034..c6773761b3f 100644
--- a/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.yaml
+++ b/input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.yaml
@@ -156,7 +156,7 @@ fleckenstein-9:
cache_l3: 25165824
ht_capable: true
instruction_set: x86-64
- microcode: '0xd0003a5'
+ microcode: '0xd0003b9'
model: Intel Xeon
other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
vendor: Intel
--
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