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Commit 0789c869 authored by JACQUOT Pierre's avatar JACQUOT Pierre
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Merge branch 'microcode-slices-fr' into 'master' 

Microcode slices fr

See merge request !1293
parents 66a140f5 09fa538c
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1 merge request!1293Microcode slices fr
Pipeline #1184109 passed with warnings
Stage: .pre
Stage: deploy-to-api-servers
Stage: check
Stage: generate-access-history
Stage: resources-explorer
Stage: .post
Pipeline: Resources Explorer

#1184110

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    data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.json
    + 1
    − 1
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    ......@@ -296,7 +296,7 @@
    "ht_capable": true,
    "instruction_set": "x86-64",
    "microarchitecture": "Ice Lake-SP",
    "microcode": "0xd0003e7",
    "microcode": "0xd000404",
    "model": "Intel Xeon",
    "other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
    "vendor": "Intel",
    ......
    data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.json
    + 1
    − 1
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    ......@@ -296,7 +296,7 @@
    "ht_capable": true,
    "instruction_set": "x86-64",
    "microarchitecture": "Ice Lake-SP",
    "microcode": "0xd0003e7",
    "microcode": "0xd000404",
    "model": "Intel Xeon",
    "other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
    "vendor": "Intel",
    ......
    data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.json
    + 1
    − 1
    View file @ 0789c869
    ......@@ -296,7 +296,7 @@
    "ht_capable": true,
    "instruction_set": "x86-64",
    "microarchitecture": "Ice Lake-SP",
    "microcode": "0xd0003e7",
    "microcode": "0xd000404",
    "model": "Intel Xeon",
    "other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
    "vendor": "Intel",
    ......
    data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.json
    + 1
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    View file @ 0789c869
    ......@@ -296,7 +296,7 @@
    "ht_capable": true,
    "instruction_set": "x86-64",
    "microarchitecture": "Ice Lake-SP",
    "microcode": "0xd0003e7",
    "microcode": "0xd000404",
    "model": "Intel Xeon",
    "other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
    "vendor": "Intel",
    ......
    data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.json
    + 1
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    View file @ 0789c869
    ......@@ -296,7 +296,7 @@
    "ht_capable": true,
    "instruction_set": "x86-64",
    "microarchitecture": "Ice Lake-SP",
    "microcode": "0xd0003b9",
    "microcode": "0xd000404",
    "model": "Intel Xeon",
    "other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
    "vendor": "Intel",
    ......
    data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.json
    + 1
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    View file @ 0789c869
    ......@@ -296,7 +296,7 @@
    "ht_capable": true,
    "instruction_set": "x86-64",
    "microarchitecture": "Ice Lake-SP",
    "microcode": "0xd0003e7",
    "microcode": "0xd000404",
    "model": "Intel Xeon",
    "other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
    "vendor": "Intel",
    ......
    data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.json
    + 1
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    View file @ 0789c869
    ......@@ -296,7 +296,7 @@
    "ht_capable": true,
    "instruction_set": "x86-64",
    "microarchitecture": "Ice Lake-SP",
    "microcode": "0xd0003e7",
    "microcode": "0xd000404",
    "model": "Intel Xeon",
    "other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
    "vendor": "Intel",
    ......
    data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.json
    + 1
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    View file @ 0789c869
    ......@@ -296,7 +296,7 @@
    "ht_capable": true,
    "instruction_set": "x86-64",
    "microarchitecture": "Ice Lake-SP",
    "microcode": "0xd0003e7",
    "microcode": "0xd000404",
    "model": "Intel Xeon",
    "other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
    "vendor": "Intel",
    ......
    data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.json
    + 1
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    View file @ 0789c869
    ......@@ -296,7 +296,7 @@
    "ht_capable": true,
    "instruction_set": "x86-64",
    "microarchitecture": "Ice Lake-SP",
    "microcode": "0xd0003e7",
    "microcode": "0xd000404",
    "model": "Intel Xeon",
    "other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
    "vendor": "Intel",
    ......
    data/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.json
    + 1
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    View file @ 0789c869
    ......@@ -296,7 +296,7 @@
    "ht_capable": true,
    "instruction_set": "x86-64",
    "microarchitecture": "Ice Lake-SP",
    "microcode": "0xd0003e7",
    "microcode": "0xd000404",
    "model": "Intel Xeon",
    "other_description": "Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz",
    "vendor": "Intel",
    ......
    input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-1.yaml
    + 1
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    View file @ 0789c869
    ......@@ -177,7 +177,7 @@ fleckenstein-1:
    cache_l3: 25165824
    ht_capable: true
    instruction_set: x86-64
    microcode: '0xd0003e7'
    microcode: '0xd000404'
    model: Intel Xeon
    other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
    vendor: Intel
    ......
    input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-10.yaml
    + 1
    − 1
    View file @ 0789c869
    ......@@ -177,7 +177,7 @@ fleckenstein-10:
    cache_l3: 25165824
    ht_capable: true
    instruction_set: x86-64
    microcode: '0xd0003e7'
    microcode: '0xd000404'
    model: Intel Xeon
    other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
    vendor: Intel
    ......
    input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-2.yaml
    + 1
    − 1
    View file @ 0789c869
    ......@@ -177,7 +177,7 @@ fleckenstein-2:
    cache_l3: 25165824
    ht_capable: true
    instruction_set: x86-64
    microcode: '0xd0003e7'
    microcode: '0xd000404'
    model: Intel Xeon
    other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
    vendor: Intel
    ......
    input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-3.yaml
    + 1
    − 1
    View file @ 0789c869
    ......@@ -177,7 +177,7 @@ fleckenstein-3:
    cache_l3: 25165824
    ht_capable: true
    instruction_set: x86-64
    microcode: '0xd0003e7'
    microcode: '0xd000404'
    model: Intel Xeon
    other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
    vendor: Intel
    ......
    input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-4.yaml
    + 1
    − 1
    View file @ 0789c869
    ......@@ -177,7 +177,7 @@ fleckenstein-4:
    cache_l3: 25165824
    ht_capable: true
    instruction_set: x86-64
    microcode: '0xd0003b9'
    microcode: '0xd000404'
    model: Intel Xeon
    other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
    vendor: Intel
    ......
    input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-5.yaml
    + 1
    − 1
    View file @ 0789c869
    ......@@ -177,7 +177,7 @@ fleckenstein-5:
    cache_l3: 25165824
    ht_capable: true
    instruction_set: x86-64
    microcode: '0xd0003e7'
    microcode: '0xd000404'
    model: Intel Xeon
    other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
    vendor: Intel
    ......
    input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-6.yaml
    + 1
    − 1
    View file @ 0789c869
    ......@@ -177,7 +177,7 @@ fleckenstein-6:
    cache_l3: 25165824
    ht_capable: true
    instruction_set: x86-64
    microcode: '0xd0003e7'
    microcode: '0xd000404'
    model: Intel Xeon
    other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
    vendor: Intel
    ......
    input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-7.yaml
    + 1
    − 1
    View file @ 0789c869
    ......@@ -177,7 +177,7 @@ fleckenstein-7:
    cache_l3: 25165824
    ht_capable: true
    instruction_set: x86-64
    microcode: '0xd0003e7'
    microcode: '0xd000404'
    model: Intel Xeon
    other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
    vendor: Intel
    ......
    input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-8.yaml
    + 1
    − 1
    View file @ 0789c869
    ......@@ -177,7 +177,7 @@ fleckenstein-8:
    cache_l3: 25165824
    ht_capable: true
    instruction_set: x86-64
    microcode: '0xd0003e7'
    microcode: '0xd000404'
    model: Intel Xeon
    other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
    vendor: Intel
    ......
    input/grid5000/sites/strasbourg/clusters/fleckenstein/nodes/fleckenstein-9.yaml
    + 1
    − 1
    View file @ 0789c869
    ......@@ -177,7 +177,7 @@ fleckenstein-9:
    cache_l3: 25165824
    ht_capable: true
    instruction_set: x86-64
    microcode: '0xd0003e7'
    microcode: '0xd000404'
    model: Intel Xeon
    other_description: Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz
    vendor: Intel
    ......
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