diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000000000000000000000000000000000000..ee4031d679d18d331f32deed2e1a64cb80c8b6c5 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,6 @@ +[submodule "tools/extract-xed-instruction-database/xed"] + path = tools/extract-xed-instruction-database/xed + url = git@github.com:intelxed/xed.git +[submodule "tools/extract-xed-instruction-database/mbuild"] + path = tools/extract-xed-instruction-database/mbuild + url = git@github.com:intelxed/mbuild.git diff --git a/src/pipedream/asm/x86/instructions.py b/src/pipedream/asm/x86/instructions.py index f19d2edd8fe1bcfe5645d9eeee5ebf471b920b41..d345ac991bc9c4a3eca9f2b25bd3d3e6266f8bbd 100644 --- a/src/pipedream/asm/x86/instructions.py +++ b/src/pipedream/asm/x86/instructions.py @@ -8,9 +8,9 @@ import pipedream.utils.abc as abc from pipedream.asm import ir -from pipedream.asm.x86.operands import * -from pipedream.asm.x86.registers import * -from pipedream.asm.x86.flags import * +from pipedream.asm.x86.operands import * +from pipedream.asm.x86.registers import * +from pipedream.asm.x86.flags import * from pipedream.asm.x86 import instructions_xed __all__ = [ diff --git a/src/pipedream/micro-bench/arch/x86_sse/get_cycles.asm b/src/pipedream/micro-bench/arch/x86_sse/get_cycles.asm index 61ef4ad196a18408d3e1901402d79efdf78dbb06..3ef23f928ddea190b650d25f0bbd67ef1693b7be 100644 --- a/src/pipedream/micro-bench/arch/x86_sse/get_cycles.asm +++ b/src/pipedream/micro-bench/arch/x86_sse/get_cycles.asm @@ -7,7 +7,7 @@ get_cycles: push rbx xor rax, rax cpuid - rdtsc + rdtsc shl rdx, 32 or rax, rdx pop rbx diff --git a/src/pipedream/micro-bench/arch/x86_sse/kernel.asm b/src/pipedream/micro-bench/arch/x86_sse/kernel.asm index 2231041644993ae727a88518dab42d552d0566ea..b394d8dfd33df5037ebc186bc0f2d969b76be846 100644 --- a/src/pipedream/micro-bench/arch/x86_sse/kernel.asm +++ b/src/pipedream/micro-bench/arch/x86_sse/kernel.asm @@ -25,14 +25,14 @@ ld_vect: ; do 8 parallel loads ; hopefully this is enough to get rid of ; false dependencies - movapd xmm0, [rdi + 8 * rcx] - movapd xmm1, [rdi + 8 * rcx + 16] - movapd xmm2, [rdi + 8 * rcx + 32] - movapd xmm3, [rdi + 8 * rcx + 48] - movapd xmm4, [rdi + 8 * rcx + 64] - movapd xmm5, [rdi + 8 * rcx + 80] - movapd xmm6, [rdi + 8 * rcx + 96] - movapd xmm7, [rdi + 8 * rcx + 112] + movapd xmm0, [rdi + 8 * rcx] + movapd xmm1, [rdi + 8 * rcx + 16] + movapd xmm2, [rdi + 8 * rcx + 32] + movapd xmm3, [rdi + 8 * rcx + 48] + movapd xmm4, [rdi + 8 * rcx + 64] + movapd xmm5, [rdi + 8 * rcx + 80] + movapd xmm6, [rdi + 8 * rcx + 96] + movapd xmm7, [rdi + 8 * rcx + 112] ; each vmov loads 2 words add rcx, 16 cmp rcx, rsi @@ -69,7 +69,7 @@ ld_vect_slw: ; do 4 parallel loads ; hopefully this is enough to get rid of ; false dependencies - movapd xmm0, [rdi + 8 * rcx] + movapd xmm0, [rdi + 8 * rcx] nop nop nop diff --git a/tools/extract-xed-instruction-database/CMakeLists.txt b/tools/extract-xed-instruction-database/CMakeLists.txt index 2b7c95b0861226e037f49c0503fe92d4d6773adb..3b4dacbdb7efab72c9dc6171ae392475e7fa4bd9 100644 --- a/tools/extract-xed-instruction-database/CMakeLists.txt +++ b/tools/extract-xed-instruction-database/CMakeLists.txt @@ -1,21 +1,25 @@ - cmake_minimum_required(VERSION 3.1) +project(extract-xed-instruction-database) + find_package(OpenMP) set(WARNINGS_FLAGS -Wall -Wextra -Werror) +#set(CMAKE_C_COMPILER clang) +#set(CMAKE_CXX_COMPILER clang) if("${XED_LOCATION}" STREQUAL "") - set(DEFAULT_XED_LOCATION "/usr") + set(DEFAULT_XED_LOCATION "./xed") - message(INFO "Variable 'XED_LOCATION' not specified, using default '${DEFAULT_XED_LOCATION}'") + message("Variable 'XED_LOCATION' not specified, using default '${DEFAULT_XED_LOCATION}'") set(XED_LOCATION "${DEFAULT_XED_LOCATION}") endif() -set(XED_LIBRARY "${XED_LOCATION}/lib/libxed.a") -set(XED_INCLUDE_DIRECTORY "${XED_LOCATION}/include") +set(XED_LIBRARY "xed") +set(XED_LIBRARY_DIRECTORY "${XED_LOCATION}/obj") +set(XED_INCLUDE_DIRECTORY "${XED_LOCATION}/obj/wkit/include") -if(NOT EXISTS "${XED_LIBRARY}") +if(NOT EXISTS "${XED_LIBRARY_DIRECTORY}/libxed.a") message(FATAL_ERROR "Invalid XED_LOCATION ('${XED_LOCATION}'), could not find libxed.a") endif() if(NOT IS_DIRECTORY "${XED_INCLUDE_DIRECTORY}") @@ -29,6 +33,7 @@ add_executable(extract-xed-instruction-database utils.cpp utils.hpp ) target_link_libraries(extract-xed-instruction-database PRIVATE "${XED_LIBRARY}") +target_link_directories(extract-xed-instruction-database PRIVATE "${XED_LIBRARY_DIRECTORY}") target_include_directories(extract-xed-instruction-database PRIVATE "${XED_INCLUDE_DIRECTORY}") target_compile_options(extract-xed-instruction-database PRIVATE ${WARNINGS_FLAGS}) diff --git a/tools/extract-xed-instruction-database/Pipedream_Info.cpp b/tools/extract-xed-instruction-database/Pipedream_Info.cpp index 7d56145b8536cb1c8d23308e891809d7ffe85f55..36e913247641c71a4e8db7b6aa89c222d1dbb717 100644 --- a/tools/extract-xed-instruction-database/Pipedream_Info.cpp +++ b/tools/extract-xed-instruction-database/Pipedream_Info.cpp @@ -318,6 +318,7 @@ std::set<std::string> Pipedream::tags(XED_Decoded_Instruction inst, const Pipedr case XED_ATTRIBUTE_MEMORY_FAULT_SUPPRESSION: case XED_ATTRIBUTE_MMX_EXCEPT: case XED_ATTRIBUTE_MPX_PREFIX_ABLE: + case XED_ATTRIBUTE_MULTIDEST2: case XED_ATTRIBUTE_MULTISOURCE4: break; case XED_ATTRIBUTE_MXCSR: diff --git a/tools/extract-xed-instruction-database/XED_Info.cpp b/tools/extract-xed-instruction-database/XED_Info.cpp index 4a7963f6c8f0bad1875edb518a6d4e9282a65d4c..f72572e48be2adc67a7feeb578c6d166564d2d1f 100644 --- a/tools/extract-xed-instruction-database/XED_Info.cpp +++ b/tools/extract-xed-instruction-database/XED_Info.cpp @@ -474,9 +474,8 @@ struct XED_Regs { abort(); } - /// xed_reg_enum_t MMX_R():: - static constexpr Register_Class MMX_R = { + static constexpr const std::initializer_list<const xed_reg_enum_t> _MMX_R = { /// REG=0x0 | XED_REG_MMX0 XED_REG_MMX0, /// REG=0x1 | XED_REG_MMX1 @@ -494,7 +493,7 @@ struct XED_Regs { /// REG=0x7 | XED_REG_MMX7 XED_REG_MMX7, }; - + static constexpr Register_Class MMX_R = _MMX_R; /// ################################# @@ -504,7 +503,7 @@ struct XED_Regs { /// # When used as the MODRM.REG register /// xed_reg_enum_t MMX_B():: - static constexpr Register_Class MMX_B = { + static constexpr const std::initializer_list<const xed_reg_enum_t> _MMX_B = { /// RM=0x0 | XED_REG_MMX0 XED_REG_MMX0, /// RM=0x1 | XED_REG_MMX1 @@ -522,6 +521,7 @@ struct XED_Regs { /// RM=0x7 | XED_REG_MMX7 XED_REG_MMX7, }; + static constexpr Register_Class MMX_B = _MMX_B; /// xed_reg_enum_t GPRv_R():: @@ -641,7 +641,7 @@ struct XED_Regs { } /// xed_reg_enum_t GPR64_R():: - static constexpr Register_Class GPR64_R = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR64_R = { /// REXR=0 REG=0x0 | XED_REG_RAX XED_REG_RAX, /// REXR=0 REG=0x1 | XED_REG_RCX @@ -675,10 +675,11 @@ struct XED_Regs { /// REXR=1 REG=0x7 | XED_REG_R15 XED_REG_R15, }; + static constexpr Register_Class GPR64_R = _GPR64_R; /// xed_reg_enum_t GPR64_B():: - static constexpr Register_Class GPR64_B = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR64_B = { /// REXB=0 RM=0x0 | XED_REG_RAX XED_REG_RAX, /// REXB=0 RM=0x1 | XED_REG_RCX @@ -712,9 +713,10 @@ struct XED_Regs { /// REXB=1 RM=0x7 | XED_REG_R15 XED_REG_R15, }; + static constexpr Register_Class GPR64_B = _GPR64_B; /// xed_reg_enum_t GPR64_SB():: - static constexpr Register_Class GPR64_SB = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR64_SB = { /// REXB=0 SRM=0x0 | XED_REG_RAX XED_REG_RAX, /// REXB=0 SRM=0x1 | XED_REG_RCX @@ -748,11 +750,12 @@ struct XED_Regs { /// REXB=1 SRM=0x7 | XED_REG_R15 XED_REG_R15, }; + static constexpr Register_Class GPR64_SB = _GPR64_SB; /// ################################# /// xed_reg_enum_t GPR64_X():: - static constexpr Register_Class GPR64_X = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR64_X = { /// REXX=0 SIBINDEX=0x0 | XED_REG_RAX XED_REG_RAX, /// REXX=0 SIBINDEX=0x1 | XED_REG_RCX @@ -786,10 +789,11 @@ struct XED_Regs { /// REXX=1 SIBINDEX=0x7 | XED_REG_R15 XED_REG_R15, }; + static constexpr Register_Class GPR64_X = _GPR64_X; /// xed_reg_enum_t GPR32_R():: - static constexpr Register_Class GPR32_R = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR32_R = { /// REXR=0 REG=0x0 | XED_REG_EAX XED_REG_EAX, /// REXR=0 REG=0x1 | XED_REG_ECX @@ -823,10 +827,11 @@ struct XED_Regs { /// REXR=1 REG=0x7 | XED_REG_R15D XED_REG_R15D, }; + static constexpr Register_Class GPR32_R = _GPR32_R; /// xed_reg_enum_t GPR32_B():: - static constexpr Register_Class GPR32_B = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR32_B = { /// REXB=0 RM=0x0 | XED_REG_EAX XED_REG_EAX, /// REXB=0 RM=0x1 | XED_REG_ECX @@ -860,9 +865,10 @@ struct XED_Regs { /// REXB=1 RM=0x7 | XED_REG_R15D XED_REG_R15D, }; + static constexpr Register_Class GPR32_B = _GPR32_B; /// xed_reg_enum_t GPR32_SB():: - static constexpr Register_Class GPR32_SB = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR32_SB = { /// REXB=0 SRM=0x0 | XED_REG_EAX XED_REG_EAX, /// REXB=0 SRM=0x1 | XED_REG_ECX @@ -896,11 +902,12 @@ struct XED_Regs { /// REXB=1 SRM=0x7 | XED_REG_R15D XED_REG_R15D, }; + static constexpr Register_Class GPR32_SB = _GPR32_SB; /// ############################# /// xed_reg_enum_t GPR32_X():: - static constexpr Register_Class GPR32_X = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR32_X = { /// REXX=0 SIBINDEX=0x0 | XED_REG_EAX XED_REG_EAX, /// REXX=0 SIBINDEX=0x1 | XED_REG_ECX @@ -934,9 +941,10 @@ struct XED_Regs { /// REXX=1 SIBINDEX=0x7 | XED_REG_R15D XED_REG_R15D, }; + static constexpr Register_Class GPR32_X = _GPR32_X; /// xed_reg_enum_t GPR16_R():: - static constexpr Register_Class GPR16_R = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR16_R = { /// REXR=0 REG=0x0 | XED_REG_AX XED_REG_AX, /// REXR=0 REG=0x1 | XED_REG_CX @@ -970,10 +978,11 @@ struct XED_Regs { /// REXR=1 REG=0x7 | XED_REG_R15W XED_REG_R15W, }; + static constexpr Register_Class GPR16_R = _GPR16_R; /// xed_reg_enum_t GPR16_B():: - static constexpr Register_Class GPR16_B = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR16_B = { /// REXB=0 RM=0x0 | XED_REG_AX XED_REG_AX, /// REXB=0 RM=0x1 | XED_REG_CX @@ -1007,10 +1016,11 @@ struct XED_Regs { /// REXB=1 RM=0x7 | XED_REG_R15W XED_REG_R15W, }; + static constexpr Register_Class GPR16_B = _GPR16_B; /// xed_reg_enum_t GPR16_SB():: - static constexpr Register_Class GPR16_SB = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR16_SB = { /// REXB=0 SRM=0x0 | XED_REG_AX XED_REG_AX, /// REXB=0 SRM=0x1 | XED_REG_CX @@ -1044,9 +1054,10 @@ struct XED_Regs { /// REXB=1 SRM=0x7 | XED_REG_R15W XED_REG_R15W, }; + static constexpr Register_Class GPR16_SB = _GPR16_SB; /// xed_reg_enum_t GPR8_R():: - static constexpr Register_Class GPR8_R_REX0 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR8_R_REX0 = { /// REXR=0 REG=0x0 | XED_REG_AL XED_REG_AL, /// REXR=0 REG=0x1 | XED_REG_CL @@ -1064,8 +1075,9 @@ struct XED_Regs { /// REXR=0 REG=0x7 REX=0 | XED_REG_BH XED_REG_BH, }; + static constexpr Register_Class GPR8_R_REX0 = _GPR8_R_REX0; - static constexpr Register_Class GPR8_R_REX1 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR8_R_REX1 = { /// REXR=0 REG=0x0 | XED_REG_AL XED_REG_AL, /// REXR=0 REG=0x1 | XED_REG_CL @@ -1099,13 +1111,14 @@ struct XED_Regs { /// REXR=1 REG=0x7 | XED_REG_R15B XED_REG_R15B, }; + static constexpr Register_Class GPR8_R_REX1 = _GPR8_R_REX1; static constexpr Register_Class GPR8_R(bool allow_rex) { return allow_rex ? GPR8_R_REX1 : GPR8_R_REX0; } /// xed_reg_enum_t GPR8_B():: - static constexpr Register_Class GPR8_B_REX0 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR8_B_REX0 = { /// REXB=0 RM=0x0 | XED_REG_AL XED_REG_AL, /// REXB=0 RM=0x1 | XED_REG_CL @@ -1123,9 +1136,10 @@ struct XED_Regs { /// REXB=0 RM=0x7 REX=0 | XED_REG_BH XED_REG_BH, }; + static constexpr Register_Class GPR8_B_REX0 = _GPR8_B_REX0; /// xed_reg_enum_t GPR8_B():: - static constexpr Register_Class GPR8_B_REX1 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR8_B_REX1 = { /// REXB=0 RM=0x0 | XED_REG_AL XED_REG_AL, /// REXB=0 RM=0x1 | XED_REG_CL @@ -1159,6 +1173,7 @@ struct XED_Regs { /// REXB=1 RM=0x7 | XED_REG_R15B XED_REG_R15B, }; + static constexpr Register_Class GPR8_B_REX1 = _GPR8_B_REX1; /// xed_reg_enum_t GPR8_B():: static constexpr Register_Class GPR8_B(bool allow_rex) { @@ -1166,7 +1181,7 @@ struct XED_Regs { } /// xed_reg_enum_t GPR8_SB():: - static constexpr Register_Class GPR8_SB_REX0 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR8_SB_REX0 = { /// REXB=0 SRM=0x0 | XED_REG_AL XED_REG_AL, /// REXB=0 SRM=0x1 | XED_REG_CL @@ -1184,9 +1199,10 @@ struct XED_Regs { /// REXB=0 SRM=0x7 REX=0 | XED_REG_BH XED_REG_BH, }; + static constexpr Register_Class GPR8_SB_REX0 = _GPR8_SB_REX0; /// xed_reg_enum_t GPR8_SB():: - static constexpr Register_Class GPR8_SB_REX1 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _GPR8_SB_REX1 = { /// REXB=0 SRM=0x0 | XED_REG_AL XED_REG_AL, /// REXB=0 SRM=0x1 | XED_REG_CL @@ -1220,6 +1236,7 @@ struct XED_Regs { /// REXB=1 SRM=0x7 | XED_REG_R15B XED_REG_R15B, }; + static constexpr Register_Class GPR8_SB_REX1 = _GPR8_SB_REX1; /// xed_reg_enum_t GPR8_SB():: static constexpr Register_Class GPR8_SB(bool allow_rex) { @@ -1227,7 +1244,7 @@ struct XED_Regs { } /// xed_reg_enum_t X87():: - static constexpr Register_Class X87 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _X87 = { /// RM=0x0 | XED_REG_ST0 XED_REG_ST0, /// RM=0x1 | XED_REG_ST1 @@ -1245,6 +1262,7 @@ struct XED_Regs { /// RM=0x7 | XED_REG_ST7 XED_REG_ST7, }; + static constexpr Register_Class X87 = _X87; /// xed_reg_enum_t XMM_R():: static constexpr Register_Class XMM_R(unsigned cpu_mode) { @@ -1264,7 +1282,7 @@ struct XED_Regs { /// xed_reg_enum_t XMM_R_32():: - static constexpr Register_Class XMM_R_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _XMM_R_32 = { /// REG=0x0 | XED_REG_XMM0 XED_REG_XMM0, /// REG=0x1 | XED_REG_XMM1 @@ -1282,10 +1300,11 @@ struct XED_Regs { /// REG=0x7 | XED_REG_XMM7 XED_REG_XMM7, }; + static constexpr Register_Class XMM_R_32 = _XMM_R_32; /// xed_reg_enum_t XMM_R_64():: - static constexpr Register_Class XMM_R_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _XMM_R_64 = { /// REXR=0 REG=0x0 | XED_REG_XMM0 XED_REG_XMM0, /// REXR=0 REG=0x1 | XED_REG_XMM1 @@ -1319,6 +1338,7 @@ struct XED_Regs { /// REXR=1 REG=0x7 | XED_REG_XMM15 XED_REG_XMM15, }; + static constexpr Register_Class XMM_R_64 = _XMM_R_64; /// xed_reg_enum_t XMM_B():: @@ -1338,7 +1358,7 @@ struct XED_Regs { } /// xed_reg_enum_t XMM_B_32():: - static constexpr Register_Class XMM_B_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _XMM_B_32 = { /// RM=0x0 | XED_REG_XMM0 XED_REG_XMM0, /// RM=0x1 | XED_REG_XMM1 @@ -1356,9 +1376,10 @@ struct XED_Regs { /// RM=0x7 | XED_REG_XMM7 XED_REG_XMM7, }; + static constexpr Register_Class XMM_B_32 = _XMM_B_32; /// xed_reg_enum_t XMM_B_64():: - static constexpr Register_Class XMM_B_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _XMM_B_64 = { /// REXB=0 RM=0x0 | XED_REG_XMM0 XED_REG_XMM0, /// REXB=0 RM=0x1 | XED_REG_XMM1 @@ -1392,6 +1413,7 @@ struct XED_Regs { /// REXB=1 RM=0x7 | XED_REG_XMM15 XED_REG_XMM15, }; + static constexpr Register_Class XMM_B_64 = _XMM_B_64; /// xed_reg_enum_t VGPR32_B():: static constexpr Register_Class VGPR32_B(unsigned cpu_mode) { @@ -1420,7 +1442,7 @@ struct XED_Regs { } /// xed_reg_enum_t VGPR32_N_32():: - static constexpr Register_Class VGPR32_N_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _VGPR32_N_32 = { /// VEXDEST210=7 | XED_REG_EAX XED_REG_EAX, /// VEXDEST210=6 | XED_REG_ECX @@ -1438,9 +1460,10 @@ struct XED_Regs { /// VEXDEST210=0 | XED_REG_EDI XED_REG_EDI, }; + static constexpr Register_Class VGPR32_N_32 = _VGPR32_N_32; /// xed_reg_enum_t VGPR32_N_64():: - static constexpr Register_Class VGPR32_N_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _VGPR32_N_64 = { /// VEXDEST3=1 VEXDEST210=7 | XED_REG_EAX XED_REG_EAX, /// VEXDEST3=1 VEXDEST210=6 | XED_REG_ECX @@ -1474,9 +1497,10 @@ struct XED_Regs { /// VEXDEST3=0 VEXDEST210=0 | XED_REG_R15D XED_REG_R15D, }; + static constexpr Register_Class VGPR32_N_64 = _VGPR32_N_64; /// xed_reg_enum_t VGPR64_N():: - static constexpr Register_Class VGPR64_N = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _VGPR64_N = { /// VEXDEST3=1 VEXDEST210=7 | XED_REG_RAX XED_REG_RAX, /// VEXDEST3=1 VEXDEST210=6 | XED_REG_RCX @@ -1510,9 +1534,10 @@ struct XED_Regs { /// VEXDEST3=0 VEXDEST210=0 | XED_REG_R15 XED_REG_R15, }; + static constexpr Register_Class VGPR64_N = _VGPR64_N; /// xed_reg_enum_t VGPR32_R_32():: - static constexpr Register_Class VGPR32_R_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _VGPR32_R_32 = { /// REG=0 | XED_REG_EAX XED_REG_EAX, /// REG=1 | XED_REG_ECX @@ -1530,9 +1555,10 @@ struct XED_Regs { /// REG=7 | XED_REG_EDI XED_REG_EDI, }; + static constexpr Register_Class VGPR32_R_32 = _VGPR32_R_32; /// xed_reg_enum_t VGPR32_R_64():: - static constexpr Register_Class VGPR32_R_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _VGPR32_R_64 = { /// REXR=0 REG=0 | XED_REG_EAX XED_REG_EAX, /// REXR=0 REG=1 | XED_REG_ECX @@ -1566,9 +1592,10 @@ struct XED_Regs { /// REXR=1 REG=7 | XED_REG_R15D XED_REG_R15D, }; + static constexpr Register_Class VGPR32_R_64 = _VGPR32_R_64; /// xed_reg_enum_t VGPR64_R():: - static constexpr Register_Class VGPR64_R = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _VGPR64_R = { /// REXR=0 REG=0 | XED_REG_RAX XED_REG_RAX, /// REXR=0 REG=1 | XED_REG_RCX @@ -1602,9 +1629,10 @@ struct XED_Regs { /// REXR=1 REG=7 | XED_REG_R15 XED_REG_R15, }; + static constexpr Register_Class VGPR64_R = _VGPR64_R; /// xed_reg_enum_t VGPR32_B_32():: - static constexpr Register_Class VGPR32_B_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _VGPR32_B_32 = { /// RM=0 | XED_REG_EAX XED_REG_EAX, /// RM=1 | XED_REG_ECX @@ -1622,9 +1650,10 @@ struct XED_Regs { /// RM=7 | XED_REG_EDI XED_REG_EDI, }; + static constexpr Register_Class VGPR32_B_32 = _VGPR32_B_32; /// xed_reg_enum_t VGPR32_B_64():: - static constexpr Register_Class VGPR32_B_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _VGPR32_B_64 = { /// REXB=0 RM=0 | XED_REG_EAX XED_REG_EAX, /// REXB=0 RM=1 | XED_REG_ECX @@ -1658,9 +1687,10 @@ struct XED_Regs { /// REXB=1 RM=7 | XED_REG_R15D XED_REG_R15D, }; + static constexpr Register_Class VGPR32_B_64 = _VGPR32_B_64; /// xed_reg_enum_t VGPR64_B():: - static constexpr Register_Class VGPR64_B = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _VGPR64_B = { /// REXB=0 RM=0 | XED_REG_RAX XED_REG_RAX, /// REXB=0 RM=1 | XED_REG_RCX @@ -1694,6 +1724,7 @@ struct XED_Regs { /// REXB=1 RM=7 | XED_REG_R15 XED_REG_R15, }; + static constexpr Register_Class VGPR64_B = _VGPR64_B; /// xed_reg_enum_t VGPRy_N():: static constexpr Register_Class VGPRy_N(int EOSZ, unsigned cpu_mode) { @@ -1738,7 +1769,7 @@ struct XED_Regs { } /// xed_reg_enum_t XMM_R3_32():: - static constexpr Register_Class XMM_R3_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _XMM_R3_32 = { /// REG=0 | XED_REG_XMM0 XED_REG_XMM0, /// REG=1 | XED_REG_XMM1 @@ -1756,9 +1787,10 @@ struct XED_Regs { /// REG=7 | XED_REG_XMM7 XED_REG_XMM7, }; + static constexpr Register_Class XMM_R3_32 = _XMM_R3_32; /// xed_reg_enum_t XMM_R3_64():: - static constexpr Register_Class XMM_R3_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _XMM_R3_64 = { /// REXRR=0 REXR=0 REG=0 | XED_REG_XMM0 XED_REG_XMM0, /// REXRR=0 REXR=0 REG=1 | XED_REG_XMM1 @@ -1824,6 +1856,7 @@ struct XED_Regs { /// REXRR=1 REXR=1 REG=7 | XED_REG_XMM31 XED_REG_XMM31, }; + static constexpr Register_Class XMM_R3_64 = _XMM_R3_64; /// xed_reg_enum_t YMM_R3():: static constexpr Register_Class YMM_R3(unsigned cpu_mode) { @@ -1839,7 +1872,7 @@ struct XED_Regs { } /// xed_reg_enum_t YMM_R3_32():: - static constexpr Register_Class YMM_R3_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _YMM_R3_32 = { /// REG=0 | XED_REG_YMM0 XED_REG_YMM0, /// REG=1 | XED_REG_YMM1 @@ -1857,9 +1890,10 @@ struct XED_Regs { /// REG=7 | XED_REG_YMM7 XED_REG_YMM7, }; + static constexpr Register_Class YMM_R3_32 = _YMM_R3_32; /// xed_reg_enum_t YMM_R3_64():: - static constexpr Register_Class YMM_R3_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _YMM_R3_64 = { /// REXRR=0 REXR=0 REG=0 | XED_REG_YMM0 XED_REG_YMM0, /// REXRR=0 REXR=0 REG=1 | XED_REG_YMM1 @@ -1925,6 +1959,7 @@ struct XED_Regs { /// REXRR=1 REXR=1 REG=7 | XED_REG_YMM31 XED_REG_YMM31, }; + static constexpr Register_Class YMM_R3_64 = _YMM_R3_64; /// xed_reg_enum_t ZMM_R3():: @@ -1941,7 +1976,7 @@ struct XED_Regs { } /// xed_reg_enum_t ZMM_R3_32():: - static constexpr Register_Class ZMM_R3_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _ZMM_R3_32 = { /// REG=0 | XED_REG_ZMM0 XED_REG_ZMM0, /// REG=1 | XED_REG_ZMM1 @@ -1959,9 +1994,10 @@ struct XED_Regs { /// REG=7 | XED_REG_ZMM7 XED_REG_ZMM7, }; + static constexpr Register_Class ZMM_R3_32 = _ZMM_R3_32; /// xed_reg_enum_t ZMM_R3_64():: - static constexpr Register_Class ZMM_R3_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _ZMM_R3_64 = { /// REXRR=0 REXR=0 REG=0 | XED_REG_ZMM0 XED_REG_ZMM0, /// REXRR=0 REXR=0 REG=1 | XED_REG_ZMM1 @@ -2027,6 +2063,7 @@ struct XED_Regs { /// REXRR=1 REXR=1 REG=7 | XED_REG_ZMM31 XED_REG_ZMM31, }; + static constexpr Register_Class ZMM_R3_64 = _ZMM_R3_64; /// xed_reg_enum_t XMM_B3():: static constexpr Register_Class XMM_B3(unsigned cpu_mode) { @@ -2042,7 +2079,7 @@ struct XED_Regs { } /// xed_reg_enum_t XMM_B3_32():: - static constexpr Register_Class XMM_B3_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _XMM_B3_32 = { /// RM=0 | XED_REG_XMM0 XED_REG_XMM0, /// RM=1 | XED_REG_XMM1 @@ -2060,9 +2097,10 @@ struct XED_Regs { /// RM=7 | XED_REG_XMM7 XED_REG_XMM7, }; + static constexpr Register_Class XMM_B3_32 = _XMM_B3_32; /// xed_reg_enum_t XMM_B3_64():: - static constexpr Register_Class XMM_B3_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _XMM_B3_64 = { /// REXX=0 REXB=0 RM=0 | XED_REG_XMM0 XED_REG_XMM0, /// REXX=0 REXB=0 RM=1 | XED_REG_XMM1 @@ -2128,6 +2166,7 @@ struct XED_Regs { /// REXX=1 REXB=1 RM=7 | XED_REG_XMM31 XED_REG_XMM31, }; + static constexpr Register_Class XMM_B3_64 = _XMM_B3_64; /// xed_reg_enum_t YMM_B3():: static constexpr Register_Class YMM_B3(unsigned cpu_mode) { @@ -2143,7 +2182,7 @@ struct XED_Regs { } /// xed_reg_enum_t YMM_B3_32():: - static constexpr Register_Class YMM_B3_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _YMM_B3_32 = { /// RM=0 | XED_REG_YMM0 XED_REG_YMM0, /// RM=1 | XED_REG_YMM1 @@ -2161,9 +2200,10 @@ struct XED_Regs { /// RM=7 | XED_REG_YMM7 XED_REG_YMM7, }; + static constexpr Register_Class YMM_B3_32 = _YMM_B3_32; /// xed_reg_enum_t YMM_B3_64():: - static constexpr Register_Class YMM_B3_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _YMM_B3_64 = { /// REXX=0 REXB=0 RM=0 | XED_REG_YMM0 XED_REG_YMM0, /// REXX=0 REXB=0 RM=1 | XED_REG_YMM1 @@ -2229,6 +2269,7 @@ struct XED_Regs { /// REXX=1 REXB=1 RM=7 | XED_REG_YMM31 XED_REG_YMM31, }; + static constexpr Register_Class YMM_B3_64 = _YMM_B3_64; /// xed_reg_enum_t ZMM_B3():: static constexpr Register_Class ZMM_B3(unsigned cpu_mode) { @@ -2244,7 +2285,7 @@ struct XED_Regs { } /// xed_reg_enum_t ZMM_B3_32():: - static constexpr Register_Class ZMM_B3_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _ZMM_B3_32 = { /// RM=0 | XED_REG_ZMM0 XED_REG_ZMM0, /// RM=1 | XED_REG_ZMM1 @@ -2262,9 +2303,10 @@ struct XED_Regs { /// RM=7 | XED_REG_ZMM7 XED_REG_ZMM7, }; + static constexpr Register_Class ZMM_B3_32 = _ZMM_B3_32; /// xed_reg_enum_t ZMM_B3_64():: - static constexpr Register_Class ZMM_B3_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _ZMM_B3_64 = { /// REXX=0 REXB=0 RM=0 | XED_REG_ZMM0 XED_REG_ZMM0, /// REXX=0 REXB=0 RM=1 | XED_REG_ZMM1 @@ -2330,6 +2372,7 @@ struct XED_Regs { /// REXX=1 REXB=1 RM=7 | XED_REG_ZMM31 XED_REG_ZMM31, }; + static constexpr Register_Class ZMM_B3_64 = _ZMM_B3_64; /// xed_reg_enum_t XMM_SE():: static constexpr Register_Class XMM_SE(unsigned cpu_mode) { @@ -2345,7 +2388,7 @@ struct XED_Regs { } /// xed_reg_enum_t XMM_SE64():: - static constexpr Register_Class XMM_SE64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _XMM_SE64 = { /// ESRC=0x0 | XED_REG_XMM0 XED_REG_XMM0, /// ESRC=0x1 | XED_REG_XMM1 @@ -2379,9 +2422,10 @@ struct XED_Regs { /// ESRC=0xF | XED_REG_XMM15 XED_REG_XMM15, }; + static constexpr Register_Class XMM_SE64 = _XMM_SE64; /// xed_reg_enum_t XMM_SE32():: - static constexpr Register_Class XMM_SE32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _XMM_SE32 = { /// # ignoring the high bit in non64b modes. Really just 0...7 /// ESRC=0x8 | OUTREG=XED_REG_XMM0 XED_REG_XMM0, @@ -2400,6 +2444,7 @@ struct XED_Regs { /// ESRC=0xF | OUTREG=XED_REG_XMM7 XED_REG_XMM7, }; + static constexpr Register_Class XMM_SE32 = _XMM_SE32; /// xed_reg_enum_t YMM_SE():: static constexpr Register_Class YMM_SE(unsigned cpu_mode) { @@ -2415,7 +2460,7 @@ struct XED_Regs { } /// xed_reg_enum_t YMM_SE64():: - static constexpr Register_Class YMM_SE64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _YMM_SE64 = { /// ESRC=0x0 | XED_REG_YMM0 XED_REG_YMM0, /// ESRC=0x1 | XED_REG_YMM1 @@ -2449,9 +2494,10 @@ struct XED_Regs { /// ESRC=0xF | XED_REG_YMM15 XED_REG_YMM15, }; + static constexpr Register_Class YMM_SE64 = _YMM_SE64; /// xed_reg_enum_t YMM_SE32():: - static constexpr Register_Class YMM_SE32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _YMM_SE32 = { /// # ignoring the high bit in non64b modes. Really just 0...7 /// ESRC=0x8 | OUTREG=XED_REG_YMM0 XED_REG_YMM0, @@ -2470,6 +2516,7 @@ struct XED_Regs { /// ESRC=0xF | OUTREG=XED_REG_YMM7 XED_REG_YMM7, }; + static constexpr Register_Class YMM_SE32 = _YMM_SE32; /// xed_reg_enum_t XMM_N():: static constexpr Register_Class XMM_N(unsigned cpu_mode) { @@ -2485,7 +2532,7 @@ struct XED_Regs { } /// xed_reg_enum_t XMM_N_32():: - static constexpr Register_Class XMM_N_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _XMM_N_32 = { /// VEXDEST210=7 | XED_REG_XMM0 XED_REG_XMM0, /// VEXDEST210=6 | XED_REG_XMM1 @@ -2503,9 +2550,10 @@ struct XED_Regs { /// VEXDEST210=0 | XED_REG_XMM7 XED_REG_XMM7, }; + static constexpr Register_Class XMM_N_32 = _XMM_N_32; /// xed_reg_enum_t XMM_N_64():: - static constexpr Register_Class XMM_N_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _XMM_N_64 = { /// VEXDEST3=1 VEXDEST210=7 | XED_REG_XMM0 XED_REG_XMM0, /// VEXDEST3=1 VEXDEST210=6 | XED_REG_XMM1 @@ -2539,6 +2587,7 @@ struct XED_Regs { /// VEXDEST3=0 VEXDEST210=0 | XED_REG_XMM15 XED_REG_XMM15, }; + static constexpr Register_Class XMM_N_64 = _XMM_N_64; /// xed_reg_enum_t YMM_N():: static constexpr Register_Class YMM_N(unsigned cpu_mode) { @@ -2554,7 +2603,7 @@ struct XED_Regs { } /// xed_reg_enum_t YMM_N_32():: - static constexpr Register_Class YMM_N_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _YMM_N_32 = { /// VEXDEST210=7 | XED_REG_YMM0 XED_REG_YMM0, /// VEXDEST210=6 | XED_REG_YMM1 @@ -2572,9 +2621,10 @@ struct XED_Regs { /// VEXDEST210=0 | XED_REG_YMM7 XED_REG_YMM7, }; + static constexpr Register_Class YMM_N_32 = _YMM_N_32; /// xed_reg_enum_t YMM_N_64():: - static constexpr Register_Class YMM_N_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _YMM_N_64 = { /// VEXDEST3=1 VEXDEST210=7 | XED_REG_YMM0 XED_REG_YMM0, /// VEXDEST3=1 VEXDEST210=6 | XED_REG_YMM1 @@ -2608,6 +2658,7 @@ struct XED_Regs { /// VEXDEST3=0 VEXDEST210=0 | XED_REG_YMM15 XED_REG_YMM15, }; + static constexpr Register_Class YMM_N_64 = _YMM_N_64; /// xed_reg_enum_t YMM_R():: static constexpr Register_Class YMM_R(unsigned cpu_mode) { @@ -2623,7 +2674,7 @@ struct XED_Regs { } /// xed_reg_enum_t YMM_R_32():: - static constexpr Register_Class YMM_R_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _YMM_R_32 = { /// REG=0 | XED_REG_YMM0 XED_REG_YMM0, /// REG=1 | XED_REG_YMM1 @@ -2641,9 +2692,10 @@ struct XED_Regs { /// REG=7 | XED_REG_YMM7 XED_REG_YMM7, }; + static constexpr Register_Class YMM_R_32 = _YMM_R_32; /// xed_reg_enum_t YMM_R_64():: - static constexpr Register_Class YMM_R_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _YMM_R_64 = { /// REXR=0 REG=0 | XED_REG_YMM0 XED_REG_YMM0, /// REXR=0 REG=1 | XED_REG_YMM1 @@ -2677,6 +2729,7 @@ struct XED_Regs { /// REXR=1 REG=7 | XED_REG_YMM15 XED_REG_YMM15, }; + static constexpr Register_Class YMM_R_64 = _YMM_R_64; /// xed_reg_enum_t YMM_B():: static constexpr Register_Class YMM_B(unsigned cpu_mode) { @@ -2692,7 +2745,7 @@ struct XED_Regs { } /// xed_reg_enum_t YMM_B_32():: - static constexpr Register_Class YMM_B_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _YMM_B_32 = { /// RM=0 | XED_REG_YMM0 XED_REG_YMM0, /// RM=1 | XED_REG_YMM1 @@ -2710,9 +2763,10 @@ struct XED_Regs { /// RM=7 | XED_REG_YMM7 XED_REG_YMM7, }; + static constexpr Register_Class YMM_B_32 = _YMM_B_32; /// xed_reg_enum_t YMM_B_64():: - static constexpr Register_Class YMM_B_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _YMM_B_64 = { /// REXB=0 RM=0 | XED_REG_YMM0 XED_REG_YMM0, /// REXB=0 RM=1 | XED_REG_YMM1 @@ -2746,6 +2800,7 @@ struct XED_Regs { /// REXB=1 RM=7 | XED_REG_YMM15 XED_REG_YMM15, }; + static constexpr Register_Class YMM_B_64 = _YMM_B_64; /// xed_reg_enum_t XMM_N3():: static constexpr Register_Class XMM_N3(unsigned cpu_mode) { @@ -2761,7 +2816,7 @@ struct XED_Regs { } /// xed_reg_enum_t XMM_N3_32():: - static constexpr Register_Class XMM_N3_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _XMM_N3_32 = { /// VEXDEST210=7 | XED_REG_XMM0 XED_REG_XMM0, /// VEXDEST210=6 | XED_REG_XMM1 @@ -2779,9 +2834,10 @@ struct XED_Regs { /// VEXDEST210=0 | XED_REG_XMM7 XED_REG_XMM7, }; + static constexpr Register_Class XMM_N3_32 = _XMM_N3_32; /// xed_reg_enum_t XMM_N3_64():: - static constexpr Register_Class XMM_N3_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _XMM_N3_64 = { /// VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | XED_REG_XMM0 XED_REG_XMM0, /// VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | XED_REG_XMM1 @@ -2847,6 +2903,7 @@ struct XED_Regs { /// VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | XED_REG_XMM31 XED_REG_XMM31, }; + static constexpr Register_Class XMM_N3_64 = _XMM_N3_64; /// xed_reg_enum_t YMM_N3():: static constexpr Register_Class YMM_N3(unsigned cpu_mode) { @@ -2862,7 +2919,7 @@ struct XED_Regs { } /// xed_reg_enum_t YMM_N3_32():: - static constexpr Register_Class YMM_N3_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _YMM_N3_32 = { /// VEXDEST210=7 | XED_REG_YMM0 XED_REG_YMM0, /// VEXDEST210=6 | XED_REG_YMM1 @@ -2880,9 +2937,10 @@ struct XED_Regs { /// VEXDEST210=0 | XED_REG_YMM7 XED_REG_YMM7, }; + static constexpr Register_Class YMM_N3_32 = _YMM_N3_32; /// xed_reg_enum_t YMM_N3_64():: - static constexpr Register_Class YMM_N3_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _YMM_N3_64 = { /// VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | XED_REG_YMM0 XED_REG_YMM0, /// VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | XED_REG_YMM1 @@ -2948,6 +3006,7 @@ struct XED_Regs { /// VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | XED_REG_YMM31 XED_REG_YMM31, }; + static constexpr Register_Class YMM_N3_64 = _YMM_N3_64; /// xed_reg_enum_t ZMM_N3():: static constexpr Register_Class ZMM_N3(unsigned cpu_mode) { @@ -2963,7 +3022,7 @@ struct XED_Regs { } /// xed_reg_enum_t ZMM_N3_32():: - static constexpr Register_Class ZMM_N3_32 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _ZMM_N3_32 = { /// VEXDEST210=7 | XED_REG_ZMM0 XED_REG_ZMM0, /// VEXDEST210=6 | XED_REG_ZMM1 @@ -2981,9 +3040,10 @@ struct XED_Regs { /// VEXDEST210=0 | XED_REG_ZMM7 XED_REG_ZMM7, }; + static constexpr Register_Class ZMM_N3_32 = _ZMM_N3_32; /// xed_reg_enum_t ZMM_N3_64():: - static constexpr Register_Class ZMM_N3_64 = { + static constexpr const std::initializer_list <const xed_reg_enum_t> _ZMM_N3_64 = { /// VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | XED_REG_ZMM0 XED_REG_ZMM0, /// VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | XED_REG_ZMM1 @@ -3049,6 +3109,7 @@ struct XED_Regs { /// VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | XED_REG_ZMM31 XED_REG_ZMM31, }; + static constexpr Register_Class ZMM_N3_64 = _ZMM_N3_64; }; } // end anonymous namespace diff --git a/tools/extract-xed-instruction-database/extract-xed-instruction-database.cpp b/tools/extract-xed-instruction-database/extract-xed-instruction-database.cpp index c589d33b75fc7a1f29f8e0a4b62f2447694639e2..a3a34212fd3ba2ef89b279939d4b198fc433986c 100644 --- a/tools/extract-xed-instruction-database/extract-xed-instruction-database.cpp +++ b/tools/extract-xed-instruction-database/extract-xed-instruction-database.cpp @@ -445,8 +445,8 @@ struct Convert { operands.push_back(op); } - - return std::move(operands); + auto ret = std::move(operands); + return ret; } /// Compute AT&T asm syntax instruction mnemonic from Pipedream_Instruction @@ -492,10 +492,8 @@ struct Convert { case XED_IFORM_MOVZX_GPRv_MEMb: return 'b'; case XED_IFORM_MOVZX_GPRv_MEMw: return 'w'; - case XED_IFORM_MOVSXD_GPRv_GPR32: return 'l'; - case XED_IFORM_MOVSXD_GPRv_MEMd: return 'l'; - - default: abort(); + case XED_IFORM_MOVSXD_GPRv_GPRz: return 'l'; + case XED_IFORM_MOVSXD_GPRv_MEMz: return 'l'; } }(); @@ -504,7 +502,6 @@ struct Convert { case Pipedream::I16: return 'w'; case Pipedream::I32: return 'l'; case Pipedream::I64: return 'q'; - default: abort(); } }(); @@ -665,9 +662,9 @@ struct Convert { case XED_ICLASS_PF2IW: case XED_ICLASS_PFACC: case XED_ICLASS_PFADD: - case XED_ICLASS_PFECMPEQ: - case XED_ICLASS_PFECMPGE: - case XED_ICLASS_PFECMPGT: + case XED_ICLASS_PFCMPEQ: + case XED_ICLASS_PFCMPGE: + case XED_ICLASS_PFCMPGT: case XED_ICLASS_PHADDD: case XED_ICLASS_PHADDSW: case XED_ICLASS_PHADDW: diff --git a/tools/extract-xed-instruction-database/mbuild b/tools/extract-xed-instruction-database/mbuild new file mode 160000 index 0000000000000000000000000000000000000000..5304b94361fccd830c0e2417535a866b79c1c297 --- /dev/null +++ b/tools/extract-xed-instruction-database/mbuild @@ -0,0 +1 @@ +Subproject commit 5304b94361fccd830c0e2417535a866b79c1c297 diff --git a/tools/extract-xed-instruction-database/utils.hpp b/tools/extract-xed-instruction-database/utils.hpp index 3e898aba8657817109312e0e371ba41c9d304f3b..2b177c9a1dbe5872812899221ac107c9dca244fe 100644 --- a/tools/extract-xed-instruction-database/utils.hpp +++ b/tools/extract-xed-instruction-database/utils.hpp @@ -19,9 +19,9 @@ template<typename T> struct Span { using const_iterator = const T*; - Span() : _size{0}, _data{0} {} + constexpr Span() : _size{0}, _data{0} {} - constexpr Span(const std::initializer_list<T> v) : _size{v.size()}, _data{v.begin()} {} + constexpr Span(const std::initializer_list<const T> v) : _size{v.size()}, _data{v.begin()} {} Span(const std::vector<T> &v) : _size{v.size()}, _data{v.data()} {} diff --git a/tools/extract-xed-instruction-database/xed b/tools/extract-xed-instruction-database/xed new file mode 160000 index 0000000000000000000000000000000000000000..afbb851b5f2f2ac6cdb6e6d9bebbaf2d4e77286d --- /dev/null +++ b/tools/extract-xed-instruction-database/xed @@ -0,0 +1 @@ +Subproject commit afbb851b5f2f2ac6cdb6e6d9bebbaf2d4e77286d