ir: correcting typo

src/pipedream/asm/ir.py

@@ -187,7 +187,7 @@ class Architecture(abc.ABC):
                       round(last[uppermost_class]*len_reg)]
             seen[uppermost_class] = big_slice_reg
             if len(big_slice_reg) < 2:
-              raise Architecture.NotEnoughRegisters
+              raise Architecture.NotEnoughRegisters()
             first[uppermost_class] = last[uppermost_class]
           else:
             big_slice_reg = seen[uppermost_class]