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Commit e0dc4f83 authored by ROKICKI Simon's avatar ROKICKI Simon

Remove mult ALU from master branch which is not supposed to handle M extension.

parent 20baa045
......@@ -227,132 +227,4 @@ public:
}
};
class MultAlu: public ALU {
public:
ac_int<32, false> quotient, remainder;
//ac_int<33, false>
ac_int<6, false> state = 0;
bool resIsNeg;
int i;
ac_int<32, false> dataAUnsigned, dataBUnsigned;
bool process(struct DCtoEx dctoEx, ac_int<32, false> &result, bool &stall){
//no need to fill in the output register fields, the first ALU has that taken care of
bool valRet = false;
if (dctoEx.opCode == RISCV_OP && dctoEx.funct7 == RISCV_OP_M) {
if (state == 0) {
dataAUnsigned.set_slc(0, dctoEx.lhs);
dataBUnsigned.set_slc(0, dctoEx.rhs);
//mult results
ac_int<32, false> resultU = dataAUnsigned * dataBUnsigned;
ac_int<32, false> resultS = dctoEx.lhs * dctoEx.rhs;
ac_int<32, false> resultSU = dctoEx.lhs * dataBUnsigned;
resIsNeg = dctoEx.lhs[31] ^ dctoEx.rhs[31];
switch (dctoEx.funct3){
case RISCV_OP_M_MUL:
result = resultS.slc<32>(0);
valRet = true;
break;
case RISCV_OP_M_MULH:
result = resultS.slc<32>(32);
valRet = true;
break;
case RISCV_OP_M_MULHSU:
result = resultSU.slc<32>(32);
valRet = true;
break;
case RISCV_OP_M_MULHU:
result = resultU.slc<32>(32);
valRet = true;
break;
case RISCV_OP_M_DIV:
if(dctoEx.lhs[31]) {
dataAUnsigned = -dctoEx.lhs;
}
if(dctoEx.rhs[31]) {
dataBUnsigned = -dctoEx.rhs;
}
//printf("Dividing %d by %d\n", dataAUnsigned, dataBUnsigned);
case RISCV_OP_M_DIVU:
if(dataBUnsigned == 0) {
result = -1;
valRet = true;
}
else {
state = 32;
quotient = 0;
remainder = 0;
}
break;
case RISCV_OP_M_REM:
if(dctoEx.lhs[31]) {
dataAUnsigned = -dctoEx.lhs;
}
if(dctoEx.rhs[31]) {
dataBUnsigned = -dctoEx.rhs;
}
//printf("Moduling %d by %d\n", dataAUnsigned, dataBUnsigned);
case RISCV_OP_M_REMU:
if(dataBUnsigned == 0) {
result = dataAUnsigned;
}
else {
state = 32;
quotient = 0;
remainder = 0;
}
break;
}
}
else {
//Loop for the division
for(i = 0; i < 4; i++)
{
state--;
remainder = remainder << 1;
remainder[0] = dataAUnsigned[state];
if(remainder >= dataBUnsigned) {
remainder = remainder - dataBUnsigned;
quotient[state] = 1;
}
}
//printf("Quotient : %d, Remainder : %d\n", quotient, remainder);
if(state == 0) {
switch(dctoEx.funct3) {
case RISCV_OP_M_DIV:
if(resIsNeg)
result = -quotient;
else
result = quotient;
valRet = true;
break;
case RISCV_OP_M_DIVU:
result = quotient;
valRet = true;
break;
case RISCV_OP_M_REM:
if(dataAUnsigned[31])
result = -remainder;
else
result = remainder;
valRet = true;
break;
case RISCV_OP_M_REMU:
result = remainder;
valRet = true;
break;
}
//printf("result : %d\n", extoMem.result);
}
}
stall |= (state != 0);
}
return valRet;
}
};
#endif /* INCLUDE_ALU_H_ */
......@@ -41,7 +41,6 @@ struct Core
MemtoWB memtoWB;
BasicAlu basicALU;
MultAlu multALU;
//memories, yay
MemoryInterface *dm, *im;
......
......@@ -454,7 +454,7 @@ void doCycle(struct Core &core, //Core containing all values
//declare temporary register file
ac_int<32, false> nextInst, multResult = 0;
ac_int<32, false> nextInst;
if (!localStall && !core.stallDm)
core.im->process(core.pc, WORD, LOAD, 0, nextInst, core.stallIm);
......@@ -462,9 +462,6 @@ void doCycle(struct Core &core, //Core containing all values
fetch(core.pc, ftoDC_temp, nextInst);
decode(core.ftoDC, dctoEx_temp, core.regFile);
core.basicALU.process(core.dctoEx, extoMem_temp, core.stallAlu); //calling ALU: execute stage
bool multUsed = core.multALU.process(core.dctoEx, multResult, core.stallAlu); //calling ALU: execute stage
if (multUsed)
extoMem_temp.result = multResult;
memory(core.extoMem, memtoWB_temp);
......
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