Commit 1b7114af authored by ROKICKI Simon's avatar ROKICKI Simon

Trying to validate caches

parent dbfb8d43
......@@ -48,6 +48,7 @@ public:
ac_int<LINE_SIZE * 8 + TAG_SIZE, false> newVal, oldVal;
ac_int<32, false> nextLevelAddr;
memOpType nextLevelOpType;
memMask nextLevelMask;
ac_int<INTERFACE_SIZE * 8, false> nextLevelDataIn;
ac_int<INTERFACE_SIZE * 8, false> nextLevelDataOut;
ac_int<40, false> cycle;
......@@ -115,9 +116,19 @@ public:
if (!nextLevelWaitOut) {
cycle++;
if (opType != NONE && cacheState == 0 && addr >= 0x30000) {
printf("Forwarding to peripherics (%x at %x)\n", addr, dataOut);
nextLevelAddr = addr;
nextLevelDataIn = dataIn;
nextLevelDataOut = dataOut;
nextLevelOpType = opType;
nextLevelMask = mask;
}
if (wasStore || cacheState == 2) {
// if (wasStore)
// printf("Storing in cache %d %d -> %x %x %x %x (addrStore is %x addrPre is %x)\n", placeStore, setStore,
// printf("Storing in cache %d %d -> %x %x %x %x (addrStore is %x addrPre is %x)\n", placeStore,
// setStore,
// valStore.template slc<32>(TAG_SIZE), valStore.template slc<32>(TAG_SIZE + 32),
// valStore.template slc<32>(TAG_SIZE + 64), valStore.template slc<32>(TAG_SIZE + 96), addrStore,
// prefetchedAddr);
......@@ -319,6 +330,7 @@ public:
nextLevelDataIn = oldVal.template slc<INTERFACE_SIZE * 8>(
(cacheState - STATE_CACHE_LAST_STORE) * INTERFACE_SIZE * 8 + TAG_SIZE);
nextLevelOpType = (isValid) ? STORE : NONE;
nextLevelMask = LONG;
// if (isValid && addr > 0x12bf4)
// printf("Writing back %x at %x\n", nextLevelDataIn, nextLevelAddr);
......@@ -334,6 +346,7 @@ public:
nextLevelAddr = (((int)addr.slc<32 - LOG_LINE_SIZE>(LOG_LINE_SIZE)) << LOG_LINE_SIZE) +
((cacheState - STATE_CACHE_LAST_LOAD - 1) << LOG_INTERFACE_SIZE);
nextLevelOpType = LOAD;
nextLevelMask = LONG;
}
}
......@@ -412,8 +425,8 @@ public:
}
}
this->nextLevel->process(nextLevelAddr, LONG, nextLevelOpType, nextLevelDataIn, nextLevelDataOut, nextLevelWaitOut,
nextLevelAddr);
this->nextLevel->process(nextLevelAddr, nextLevelMask, nextLevelOpType, nextLevelDataIn, nextLevelDataOut,
nextLevelWaitOut, nextLevelAddr);
waitOut = nextLevelWaitOut || cacheState || (wasStore && opType != NONE);
if (updateLoadedLine && cacheState != STATE_CACHE_MISS) {
......
......@@ -2,8 +2,8 @@
#define __MEMORY_INTERFACE_H__
#include <ac_int.h>
#define MEMMASK 0xffffff
// #define MEMMASK 0x3fff
// #define MEMMASK 0xffffff
#define MEMMASK 0x3fff
typedef enum { BYTE = 0, HALF, WORD, BYTE_U, HALF_U, LONG } memMask;
......
......@@ -24,12 +24,20 @@ solution library add C28SOI_SC_12_CORE_LL_ccs -file /opt/DesignKit/catapult_lib/
go libraries
directive set -CLOCKS {clk {-CLOCK_PERIOD 2 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 1.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND sync -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_ACTIVE high}}
go assembly
directive set /doCore/core/dmCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.cacheMemory:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/imCache.age:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/imCache.dataValid:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/dmCache.cacheMemory:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/dmCache.age:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/dmCache.dataValid:rsc -MAP_TO_MODULE ccs_sample_mem.ccs_ram_sync_singleport
directive set /doCore/core/imCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/globalStall:rsc -MAP_TO_MODULE {[DirectInput]}
directive set /doCore/core/core.regFile:rsc -MAP_TO_MODULE {[Register]}
directive set /doCore/core/while -PIPELINE_INIT_INTERVAL 1
......
......@@ -25,12 +25,18 @@ go libraries
directive set -TRANSACTION_DONE_SIGNAL false
directive set -CLOCKS {clk {-CLOCK_PERIOD 10.0 -CLOCK_EDGE rising -CLOCK_HIGH_TIME 5.0 -CLOCK_OFFSET 0.000000 -CLOCK_UNCERTAINTY 0.0 -RESET_KIND sync -RESET_SYNC_NAME rst -RESET_SYNC_ACTIVE high -RESET_ASYNC_NAME arst_n -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
go assembly
directive set /doCore/core/dmCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.cacheMemory:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/imCache.age:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/imCache.dataValid:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/dmCache.cacheMemory:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/dmCache.age:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/dmCache.dataValid:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/core/imCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/imCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.cacheMemory:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.age:rsc -INTERLEAVE 4
directive set /doCore/core/dmCache.dataValid:rsc -INTERLEAVE 4
directive set /doCore/globalStall:rsc -MAP_TO_MODULE {[DirectInput]}
directive set /doCore/imData:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
directive set /doCore/dmData:rsc -MAP_TO_MODULE Xilinx_RAMS.BLOCK_SPRAM_RBW
......
......@@ -862,7 +862,7 @@ void doCore(bool globalStall, ac_int<1, false>* crashFlag, ac_int<32, false> imD
CacheMemory<IncompleteMemory, 4, 16, 64> imCache = CacheMemory<IncompleteMemory, 4, 16, 64>(&imInterface, false);
CacheMemory<IncompleteMemory, 4, 16, 64> dmCache = CacheMemory<IncompleteMemory, 4, 16, 64>(&dmInterface, false);
core.im = &imCache;
core.im = &imInterface;
core.dm = &dmInterface;
core.pc = 0x00010000;
core.regFile[2] = 0x27ffc;
......@@ -874,6 +874,7 @@ void doCore(bool globalStall, ac_int<1, false>* crashFlag, ac_int<32, false> imD
doCycle(core, globalStall);
if (core.dctoEx.crashFlag) {
printf("Crash\n");
*crashFlag = 1;
return;
}
......
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