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Commit 1899e9b1 authored by ROKICKI Simon's avatar ROKICKI Simon

Modified mult alu for lowering area consumption

parent dd13b1d6
......@@ -18,11 +18,11 @@ protected:
bool wait;
public:
virtual void process(struct DCtoEx dctoEx, struct ExtoMem &extoMem, bool &stall) =0;
virtual bool process(struct DCtoEx dctoEx, ac_int<32, false> &result, bool &stall) =0;
};
class BasicAlu: public ALU {
class BasicAlu {
public:
void process(struct DCtoEx dctoEx, struct ExtoMem &extoMem, bool &stall){
stall = false;
......@@ -235,9 +235,11 @@ public:
bool resIsNeg;
ac_int<32, false> dataAUnsigned, dataBUnsigned;
void process(struct DCtoEx dctoEx, struct ExtoMem &extoMem, bool &stall){
bool process(struct DCtoEx dctoEx, ac_int<32, false> &result, bool &stall){
//no need to fill in the output register fields, the first ALU has that taken care of
if (dctoEx.opCode == RISCV_OP && dctoEx.funct7 == RISCV_OP_M) {
bool valRet = false;
if (dctoEx.opCode == RISCV_OP && dctoEx.funct7 == RISCV_OP_M) {
if (state == 0) {
......@@ -247,20 +249,24 @@ public:
ac_int<32, false> resultU = dataAUnsigned * dataBUnsigned;
ac_int<32, false> resultS = dctoEx.lhs * dctoEx.rhs;
ac_int<32, false> resultSU = dctoEx.lhs * dataBUnsigned;
resIsNeg = dctoEx.lhs[31] ^ dctoEx.rhs[31];
resIsNeg = dctoEx.lhs[31] ^ dctoEx.rhs[31];
switch (dctoEx.funct3){
case RISCV_OP_M_MUL:
extoMem.result = resultS.slc<32>(0);
result = resultS.slc<32>(0);
valRet = true;
break;
case RISCV_OP_M_MULH:
extoMem.result = resultS.slc<32>(32);
result = resultS.slc<32>(32);
valRet = true;
break;
case RISCV_OP_M_MULHSU:
extoMem.result = resultSU.slc<32>(32);
result = resultSU.slc<32>(32);
valRet = true;
break;
case RISCV_OP_M_MULHU:
extoMem.result = resultU.slc<32>(32);
result = resultU.slc<32>(32);
valRet = true;
break;
case RISCV_OP_M_DIV:
if(dctoEx.lhs[31]) {
......@@ -272,7 +278,8 @@ public:
//printf("Dividing %d by %d\n", dataAUnsigned, dataBUnsigned);
case RISCV_OP_M_DIVU:
if(dataBUnsigned == 0) {
extoMem.result = -1;
result = -1;
valRet = true;
}
else {
state = 32;
......@@ -290,7 +297,7 @@ public:
//printf("Moduling %d by %d\n", dataAUnsigned, dataBUnsigned);
case RISCV_OP_M_REMU:
if(dataBUnsigned == 0) {
extoMem.result = dataAUnsigned;
result = dataAUnsigned;
}
else {
state = 32;
......@@ -314,21 +321,25 @@ public:
switch(dctoEx.funct3) {
case RISCV_OP_M_DIV:
if(resIsNeg)
extoMem.result = -quotient;
result = -quotient;
else
extoMem.result = quotient;
result = quotient;
valRet = true;
break;
case RISCV_OP_M_DIVU:
extoMem.result = quotient;
result = quotient;
valRet = true;
break;
case RISCV_OP_M_REM:
if(dataAUnsigned[31])
extoMem.result = -remainder;
result = -remainder;
else
extoMem.result = remainder;
result = remainder;
valRet = true;
break;
case RISCV_OP_M_REMU:
extoMem.result = remainder;
result = remainder;
valRet = true;
break;
}
//printf("result : %d\n", extoMem.result);
......@@ -336,6 +347,7 @@ public:
}
stall |= (state != 0);
}
return valRet;
}
};
......
......@@ -21,7 +21,7 @@ go compile
solution library add C28SOI_SC_12_CORE_LL_ccs -file /opt/DesignKit/catapult_lib/C28SOI_SC_12_CORE_LL_ccs.lib
solution library add ST_singleport_8192x32
go libraries
directive set -CLOCKS {clk {-CLOCK_PERIOD 1.67 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 0.835 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND sync -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_ACTIVE high}}
directive set -CLOCKS {clk {-CLOCK_PERIOD 2 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 1.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND sync -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_ACTIVE high}}
go assembly
directive set /doCore/globalStall:rsc -MAP_TO_MODULE {[DirectInput]}
directive set /doCore/core/core.regFile:rsc -MAP_TO_MODULE {[Register]}
......
......@@ -454,15 +454,18 @@ void doCycle(struct Core &core, //Core containing all values
//declare temporary register file
ac_int<32, false> nextInst;
ac_int<32, false> nextInst, multResult = 0;
if (!localStall && !core.stallDm)
core.im->process(core.pc, WORD, LOAD, 0, nextInst, core.stallIm);
fetch(core.pc, ftoDC_temp, nextInst);
decode(core.ftoDC, dctoEx_temp, core.regFile);
core.basicALU.process(core.dctoEx, extoMem_temp, core.stallAlu); //calling ALU: execute stage
core.multALU.process(core.dctoEx, extoMem_temp, core.stallAlu); //calling ALU: execute stage
core.basicALU.process(core.dctoEx, extoMem_temp, core.stallAlu); //calling ALU: execute stage
bool multUsed = core.multALU.process(core.dctoEx, multResult, core.stallAlu); //calling ALU: execute stage
if (multUsed)
extoMem_temp.result = multResult;
memory(core.extoMem, memtoWB_temp);
writeback(core.memtoWB, wbOut_temp);
......
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