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Commit 1897f49a authored by ROKICKI Simon's avatar ROKICKI Simon

Apply clang format. Add the format file

parent b860b055
---
Language: Cpp
AccessModifierOffset: -2
AlignAfterOpenBracket: Align
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AlignConsecutiveDeclarations: false
AlignEscapedNewlinesLeft: false
AlignOperands: true
AlignTrailingComments: true
AllowAllParametersOfDeclarationOnNextLine: true
AllowShortBlocksOnASingleLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: Inline
AllowShortIfStatementsOnASingleLine: false
AllowShortLoopsOnASingleLine: false
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: false
BinPackArguments: true
BinPackParameters: true
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AfterControlStatement: false
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AfterNamespace: false
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AfterUnion: false
BeforeCatch: false
BeforeElse: false
IndentBraces: false
BreakBeforeBinaryOperators: None
BreakBeforeBraces: Custom
BreakBeforeTernaryOperators: true
BreakConstructorInitializersBeforeComma: true
ColumnLimit: 120
CommentPragmas: '^ IWYU pragma:'
ConstructorInitializerAllOnOneLineOrOnePerLine: true
ConstructorInitializerIndentWidth: 4
ContinuationIndentWidth: 4
Cpp11BracedListStyle: true
DerivePointerAlignment: false
DisableFormat: false
ExperimentalAutoDetectBinPacking: false
ForEachMacros: [ 'xbt_dynar_foreach', 'xbt_dict_foreach' ]
IncludeCategories:
- Regex: '^"(llvm|llvm-c|clang|clang-c)/'
Priority: 2
- Regex: '^(<|"(gtest|isl|json)/)'
Priority: 3
- Regex: '.*'
Priority: 1
IndentCaseLabels: true
IndentWidth: 2
IndentWrappedFunctionNames: false
KeepEmptyLinesAtTheStartOfBlocks: true
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: None
ObjCBlockIndentWidth: 2
ObjCSpaceAfterProperty: false
ObjCSpaceBeforeProtocolList: true
PenaltyBreakBeforeFirstCallParameter: 19
PenaltyBreakComment: 300
PenaltyBreakFirstLessLess: 120
PenaltyBreakString: 1000
PenaltyExcessCharacter: 1000000
PenaltyReturnTypeOnItsOwnLine: 60
PointerAlignment: Left
ReflowComments: true
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SpaceAfterCStyleCast: false
SpaceBeforeAssignmentOperators: true
SpaceBeforeParens: ControlStatements
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SpacesInCStyleCastParentheses: false
SpacesInParentheses: false
SpacesInSquareBrackets: false
Standard: Cpp11
TabWidth: 8
UseTab: Never
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......@@ -8,8 +8,8 @@
#ifndef INCLUDE_ALU_H_
#define INCLUDE_ALU_H_
#include <riscvISA.h>
#include <pipelineRegisters.h>
#include <riscvISA.h>
//#include <cstdio>
......@@ -18,213 +18,209 @@ protected:
bool wait;
public:
virtual bool process(struct DCtoEx dctoEx, ac_int<32, false> &result, bool &stall) =0;
virtual bool process(struct DCtoEx dctoEx, ac_int<32, false>& result, bool& stall) = 0;
};
class BasicAlu {
public:
void process(struct DCtoEx dctoEx, struct ExtoMem &extoMem, bool &stall){
stall = false;
extoMem.pc = dctoEx.pc;
extoMem.opCode = dctoEx.opCode;
extoMem.rd = dctoEx.rd;
extoMem.funct3 = dctoEx.funct3;
extoMem.we = dctoEx.we;
extoMem.isBranch = 0;
extoMem.useRd = dctoEx.useRd;
extoMem.isLongInstruction = 0;
extoMem.instruction = dctoEx.instruction;
ac_int<13, false> imm13 = 0;
imm13[12] = dctoEx.instruction[31];
imm13.set_slc(5, dctoEx.instruction.slc<6>(25));
imm13.set_slc(1, dctoEx.instruction.slc<4>(8));
imm13[11] = dctoEx.instruction[7];
ac_int<13, true> imm13_signed = 0;
imm13_signed.set_slc(0, imm13);
ac_int<5, false> shamt = dctoEx.instruction.slc<5>(20);
// switch must be in the else, otherwise external op may trigger default case
switch(dctoEx.opCode)
{
case RISCV_LUI:
extoMem.result = dctoEx.lhs;
break;
case RISCV_AUIPC:
extoMem.result = dctoEx.lhs + dctoEx.rhs;
break;
case RISCV_JAL:
//Note: in current version, the addition is made in the decode stage
//The value to store in rd (pc+4) is stored in lhs
extoMem.result = dctoEx.lhs;
break;
case RISCV_JALR:
//Note: in current version, the addition is made in the decode stage
//The value to store in rd (pc+4) is stored in lhs
extoMem.nextPC = dctoEx.rhs + dctoEx.lhs;
extoMem.isBranch = 1;
extoMem.result = dctoEx.pc+4;
break;
case RISCV_BR:
extoMem.nextPC = extoMem.pc + imm13_signed;
switch(dctoEx.funct3)
{
case RISCV_BR_BEQ:
extoMem.isBranch = (dctoEx.lhs == dctoEx.rhs);
break;
case RISCV_BR_BNE:
extoMem.isBranch = (dctoEx.lhs != dctoEx.rhs);
break;
case RISCV_BR_BLT:
extoMem.isBranch = (dctoEx.lhs < dctoEx.rhs);
break;
case RISCV_BR_BGE:
extoMem.isBranch = (dctoEx.lhs >= dctoEx.rhs);
break;
case RISCV_BR_BLTU:
extoMem.isBranch = ((ac_int<32, false>)dctoEx.lhs < (ac_int<32, false>)dctoEx.rhs);
break;
case RISCV_BR_BGEU:
extoMem.isBranch = ((ac_int<32, false>)dctoEx.lhs >= (ac_int<32, false>)dctoEx.rhs);
break;
}
break;
case RISCV_LD:
extoMem.isLongInstruction = 1;
extoMem.result = dctoEx.lhs + dctoEx.rhs;
break;
case RISCV_ST:
extoMem.datac = dctoEx.datac;
extoMem.result = dctoEx.lhs + dctoEx.rhs;
break;
case RISCV_OPI:
switch(dctoEx.funct3)
{
case RISCV_OPI_ADDI:
extoMem.result = dctoEx.lhs + dctoEx.rhs;
break;
case RISCV_OPI_SLTI:
extoMem.result = dctoEx.lhs < dctoEx.rhs;
break;
case RISCV_OPI_SLTIU:
extoMem.result = (ac_int<32, false>)dctoEx.lhs < (ac_int<32, false>)dctoEx.rhs;
break;
case RISCV_OPI_XORI:
extoMem.result = dctoEx.lhs ^ dctoEx.rhs;
break;
case RISCV_OPI_ORI:
extoMem.result = dctoEx.lhs | dctoEx.rhs;
break;
case RISCV_OPI_ANDI:
extoMem.result = dctoEx.lhs & dctoEx.rhs;
break;
case RISCV_OPI_SLLI: // cast rhs as 5 bits, otherwise generated hardware is 32 bits
// & shift amount held in the lower 5 bits (riscv spec)
extoMem.result = dctoEx.lhs << (ac_int<5, false>)dctoEx.rhs;
break;
case RISCV_OPI_SRI:
if (dctoEx.funct7.slc<1>(5)) //SRAI
extoMem.result = dctoEx.lhs >> (ac_int<5, false>)shamt;
else //SRLI
extoMem.result = (ac_int<32, false>)dctoEx.lhs >> (ac_int<5, false>)shamt;
break;
}
break;
case RISCV_OP:
if(dctoEx.funct7.slc<1>(0)) // M Extension
{
}
else{
switch(dctoEx.funct3){
case RISCV_OP_ADD:
if (dctoEx.funct7.slc<1>(5)) // SUB
extoMem.result = dctoEx.lhs - dctoEx.rhs;
else // ADD
extoMem.result = dctoEx.lhs + dctoEx.rhs;
break;
case RISCV_OP_SLL:
extoMem.result = dctoEx.lhs << (ac_int<5, false>)dctoEx.rhs;
break;
case RISCV_OP_SLT:
extoMem.result = dctoEx.lhs < dctoEx.rhs;
break;
case RISCV_OP_SLTU:
extoMem.result = (ac_int<32, false>)dctoEx.lhs < (ac_int<32, false>)dctoEx.rhs;
break;
case RISCV_OP_XOR:
extoMem.result = dctoEx.lhs ^ dctoEx.rhs;
break;
case RISCV_OP_SR:
if(dctoEx.funct7.slc<1>(5)) // SRA
extoMem.result = dctoEx.lhs >> (ac_int<5, false>)dctoEx.rhs;
else // SRL
extoMem.result = (ac_int<32, false>)dctoEx.lhs >> (ac_int<5, false>)dctoEx.rhs;
break;
case RISCV_OP_OR:
extoMem.result = dctoEx.lhs | dctoEx.rhs;
break;
case RISCV_OP_AND:
extoMem.result = dctoEx.lhs & dctoEx.rhs;
break;
}
}
break;
case RISCV_MISC_MEM: // this does nothing because all memory accesses are ordered and we have only one core
break;
case RISCV_SYSTEM:
switch(dctoEx.funct3)
{ // case 0: mret instruction, dctoEx.memValue should be 0x302
case RISCV_SYSTEM_ENV:
#ifndef __HLS__
//TODO handling syscall correctly
//extoMem.result = sim->solveSyscall(dctoEx.lhs, dctoEx.rhs, dctoEx.datac, dctoEx.datad, dctoEx.datae, exit);
#endif
break;
case RISCV_SYSTEM_CSRRW: // lhs is from csr, rhs is from reg[rs1]
extoMem.datac = dctoEx.rhs; // written back to csr
extoMem.result = dctoEx.lhs; // written back to rd
break;
case RISCV_SYSTEM_CSRRS:
extoMem.datac = dctoEx.lhs | dctoEx.rhs;
extoMem.result = dctoEx.lhs;
break;
case RISCV_SYSTEM_CSRRC:
extoMem.datac = dctoEx.lhs & ((ac_int<32, false>)~dctoEx.rhs);
extoMem.result = dctoEx.lhs;
break;
case RISCV_SYSTEM_CSRRWI:
extoMem.datac = dctoEx.rhs;
extoMem.result = dctoEx.lhs;
break;
case RISCV_SYSTEM_CSRRSI:
extoMem.datac = dctoEx.lhs | dctoEx.rhs;
extoMem.result = dctoEx.lhs;
break;
case RISCV_SYSTEM_CSRRCI:
extoMem.datac = dctoEx.lhs & ((ac_int<32, false>)~dctoEx.rhs);
extoMem.result = dctoEx.lhs;
break;
}
break;
}
//If the instruction was dropped, we ensure that isBranch is at zero
if (!dctoEx.we){
extoMem.isBranch = 0;
extoMem.useRd = 0;
}
}
void process(struct DCtoEx dctoEx, struct ExtoMem& extoMem, bool& stall)
{
stall = false;
extoMem.pc = dctoEx.pc;
extoMem.opCode = dctoEx.opCode;
extoMem.rd = dctoEx.rd;
extoMem.funct3 = dctoEx.funct3;
extoMem.we = dctoEx.we;
extoMem.isBranch = 0;
extoMem.useRd = dctoEx.useRd;
extoMem.isLongInstruction = 0;
extoMem.instruction = dctoEx.instruction;
ac_int<13, false> imm13 = 0;
imm13[12] = dctoEx.instruction[31];
imm13.set_slc(5, dctoEx.instruction.slc<6>(25));
imm13.set_slc(1, dctoEx.instruction.slc<4>(8));
imm13[11] = dctoEx.instruction[7];
ac_int<13, true> imm13_signed = 0;
imm13_signed.set_slc(0, imm13);
ac_int<5, false> shamt = dctoEx.instruction.slc<5>(20);
// switch must be in the else, otherwise external op may trigger default
// case
switch (dctoEx.opCode) {
case RISCV_LUI:
extoMem.result = dctoEx.lhs;
break;
case RISCV_AUIPC:
extoMem.result = dctoEx.lhs + dctoEx.rhs;
break;
case RISCV_JAL:
// Note: in current version, the addition is made in the decode stage
// The value to store in rd (pc+4) is stored in lhs
extoMem.result = dctoEx.lhs;
break;
case RISCV_JALR:
// Note: in current version, the addition is made in the decode stage
// The value to store in rd (pc+4) is stored in lhs
extoMem.nextPC = dctoEx.rhs + dctoEx.lhs;
extoMem.isBranch = 1;
extoMem.result = dctoEx.pc + 4;
break;
case RISCV_BR:
extoMem.nextPC = extoMem.pc + imm13_signed;
switch (dctoEx.funct3) {
case RISCV_BR_BEQ:
extoMem.isBranch = (dctoEx.lhs == dctoEx.rhs);
break;
case RISCV_BR_BNE:
extoMem.isBranch = (dctoEx.lhs != dctoEx.rhs);
break;
case RISCV_BR_BLT:
extoMem.isBranch = (dctoEx.lhs < dctoEx.rhs);
break;
case RISCV_BR_BGE:
extoMem.isBranch = (dctoEx.lhs >= dctoEx.rhs);
break;
case RISCV_BR_BLTU:
extoMem.isBranch = ((ac_int<32, false>)dctoEx.lhs < (ac_int<32, false>)dctoEx.rhs);
break;
case RISCV_BR_BGEU:
extoMem.isBranch = ((ac_int<32, false>)dctoEx.lhs >= (ac_int<32, false>)dctoEx.rhs);
break;
}
break;
case RISCV_LD:
extoMem.isLongInstruction = 1;
extoMem.result = dctoEx.lhs + dctoEx.rhs;
break;
case RISCV_ST:
extoMem.datac = dctoEx.datac;
extoMem.result = dctoEx.lhs + dctoEx.rhs;
break;
case RISCV_OPI:
switch (dctoEx.funct3) {
case RISCV_OPI_ADDI:
extoMem.result = dctoEx.lhs + dctoEx.rhs;
break;
case RISCV_OPI_SLTI:
extoMem.result = dctoEx.lhs < dctoEx.rhs;
break;
case RISCV_OPI_SLTIU:
extoMem.result = (ac_int<32, false>)dctoEx.lhs < (ac_int<32, false>)dctoEx.rhs;
break;
case RISCV_OPI_XORI:
extoMem.result = dctoEx.lhs ^ dctoEx.rhs;
break;
case RISCV_OPI_ORI:
extoMem.result = dctoEx.lhs | dctoEx.rhs;
break;
case RISCV_OPI_ANDI:
extoMem.result = dctoEx.lhs & dctoEx.rhs;
break;
case RISCV_OPI_SLLI: // cast rhs as 5 bits, otherwise generated hardware
// is 32 bits
// & shift amount held in the lower 5 bits (riscv spec)
extoMem.result = dctoEx.lhs << (ac_int<5, false>)dctoEx.rhs;
break;
case RISCV_OPI_SRI:
if (dctoEx.funct7.slc<1>(5)) // SRAI
extoMem.result = dctoEx.lhs >> (ac_int<5, false>)shamt;
else // SRLI
extoMem.result = (ac_int<32, false>)dctoEx.lhs >> (ac_int<5, false>)shamt;
break;
}
break;
case RISCV_OP:
if (dctoEx.funct7.slc<1>(0)) // M Extension
{
} else {
switch (dctoEx.funct3) {
case RISCV_OP_ADD:
if (dctoEx.funct7.slc<1>(5)) // SUB
extoMem.result = dctoEx.lhs - dctoEx.rhs;
else // ADD
extoMem.result = dctoEx.lhs + dctoEx.rhs;
break;
case RISCV_OP_SLL:
extoMem.result = dctoEx.lhs << (ac_int<5, false>)dctoEx.rhs;
break;
case RISCV_OP_SLT:
extoMem.result = dctoEx.lhs < dctoEx.rhs;
break;
case RISCV_OP_SLTU:
extoMem.result = (ac_int<32, false>)dctoEx.lhs < (ac_int<32, false>)dctoEx.rhs;
break;
case RISCV_OP_XOR:
extoMem.result = dctoEx.lhs ^ dctoEx.rhs;
break;
case RISCV_OP_SR:
if (dctoEx.funct7.slc<1>(5)) // SRA
extoMem.result = dctoEx.lhs >> (ac_int<5, false>)dctoEx.rhs;
else // SRL
extoMem.result = (ac_int<32, false>)dctoEx.lhs >> (ac_int<5, false>)dctoEx.rhs;
break;
case RISCV_OP_OR:
extoMem.result = dctoEx.lhs | dctoEx.rhs;
break;
case RISCV_OP_AND:
extoMem.result = dctoEx.lhs & dctoEx.rhs;
break;
}
}
break;
case RISCV_MISC_MEM: // this does nothing because all memory accesses are
// ordered and we have only one core
break;
case RISCV_SYSTEM:
switch (dctoEx.funct3) { // case 0: mret instruction, dctoEx.memValue
// should be 0x302
case RISCV_SYSTEM_ENV:
#ifndef __HLS__
// TODO handling syscall correctly
// extoMem.result = sim->solveSyscall(dctoEx.lhs, dctoEx.rhs,
// dctoEx.datac, dctoEx.datad, dctoEx.datae, exit);
#endif
break;
case RISCV_SYSTEM_CSRRW: // lhs is from csr, rhs is from reg[rs1]
extoMem.datac = dctoEx.rhs; // written back to csr
extoMem.result = dctoEx.lhs; // written back to rd
break;
case RISCV_SYSTEM_CSRRS:
extoMem.datac = dctoEx.lhs | dctoEx.rhs;
extoMem.result = dctoEx.lhs;
break;
case RISCV_SYSTEM_CSRRC:
extoMem.datac = dctoEx.lhs & ((ac_int<32, false>)~dctoEx.rhs);
extoMem.result = dctoEx.lhs;
break;
case RISCV_SYSTEM_CSRRWI:
extoMem.datac = dctoEx.rhs;
extoMem.result = dctoEx.lhs;
break;
case RISCV_SYSTEM_CSRRSI:
extoMem.datac = dctoEx.lhs | dctoEx.rhs;
extoMem.result = dctoEx.lhs;
break;
case RISCV_SYSTEM_CSRRCI:
extoMem.datac = dctoEx.lhs & ((ac_int<32, false>)~dctoEx.rhs);
extoMem.result = dctoEx.lhs;
break;
}
break;
}
// If the instruction was dropped, we ensure that isBranch is at zero
if (!dctoEx.we) {
extoMem.isBranch = 0;
extoMem.useRd = 0;
}
}
};
#endif /* INCLUDE_ALU_H_ */
#ifndef __BASIC_SIMULATOR_H__
#define __BASIC_SIMULATOR_H__
#include "simulator.h"
#include <map>
#include <vector>
#include "simulator.h"
class BasicSimulator : public Simulator
{
unsigned heapAddress;
std::map<ac_int<32, false>, ac_int<8, false> > imemMap;
std::map<ac_int<32, false>, ac_int<8, false> > dmemMap;
ac_int<32, false> *im, *dm;
FILE* inputFile;
FILE* outputFile;
FILE* traceFile;
class BasicSimulator : public Simulator {
unsigned heapAddress;
std::map<ac_int<32, false>, ac_int<8, false>> imemMap;
std::map<ac_int<32, false>, ac_int<8, false>> dmemMap;
ac_int<32, false>*im, *dm;
FILE* inputFile;
FILE* outputFile;
FILE* traceFile;
public:
BasicSimulator(const char* binaryFile, std::vector<std::string>, const char* inFile, const char* outFile, const char *tFile );
~BasicSimulator();
BasicSimulator(const char* binaryFile, std::vector<std::string>, const char* inFile, const char* outFile,
const char* tFile);
~BasicSimulator();
protected:
void fillMemory();
void printCycle();
void printStat(){};
void extend(){};
void solveSyscall();
void insertInstructionMemoryMap(ac_int<32, false> addr, ac_int<8, false> value);
void insertDataMemoryMap(ac_int<32, false> addr, ac_int<8, false> value);
ac_int<32, true> doRead(ac_int<32, false> file, ac_int<32, false> bufferAddr, ac_int<32, false> size);
ac_int<32, true> doWrite(ac_int<32, false> file, ac_int<32, false> bufferAddr, ac_int<32, false> size);
ac_int<32, true> doOpen(ac_int<32, false> name, ac_int<32, false> flags, ac_int<32, false> mode);
ac_int<32, true> doOpenat(ac_int<32, false> dir, ac_int<32, false> name, ac_int<32, false> flags, ac_int<32, false> mode);
ac_int<32, true> doLseek(ac_int<32, false> file, ac_int<32, false> ptr, ac_int<32, false> dir);
ac_int<32, true> doClose(ac_int<32, false> file);
ac_int<32, true> doStat(ac_int<32, false> filename, ac_int<32, false> ptr);
ac_int<32, true> doSbrk(ac_int<32, false> value);
ac_int<32, true> doGettimeofday(ac_int<32, false> timeValPtr);
ac_int<32, true> doUnlink(ac_int<32, false> path);
ac_int<32, true> doFstat(ac_int<32, false> file, ac_int<32, false> stataddr);
void stb(ac_int<32, false> addr, ac_int<8, true> value);
void sth(ac_int<32, false> addr, ac_int<16, true> value);
void stw(ac_int<32, false> addr, ac_int<32, true> value);
void std(ac_int<32, false> addr, ac_int<64, true> value);
ac_int<8, true> ldb(ac_int<32, false> addr);
ac_int<16, true> ldh(ac_int<32, false> addr);
ac_int<32, true> ldw(ac_int<32, false> addr);
ac_int<32, true> ldd(ac_int<32, false> addr);
void fillMemory();
void printCycle();
void printStat(){};
void extend(){};
void solveSyscall();
void insertInstructionMemoryMap(ac_int<32, false> addr, ac_int<8, false> value);
void insertDataMemoryMap(ac_int<32, false> addr, ac_int<8, false> value);
ac_int<32, true> doRead(ac_int<32, false> file, ac_int<32, false> bufferAddr, ac_int<32, false> size);
ac_int<32, true> doWrite(ac_int<32, false> file, ac_int<32, false> bufferAddr, ac_int<32, false> size);